A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse
- 4 April 2024
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Solid-State Circuits Letters
- Vol. 7, 143-146
Abstract
The design and measurement of a time-domain analog spiking neuron is described. The proposed neuron leverages time-domain processing using voltage-controlled oscillators (VCOs) and a time-domain comparator to integrate the input spike and trigger the output spike. A novel leaky circuit uses a phase-locked loop (PLL) to drive the phase difference between the two VCOs toward zero. A weighted capacitive digital-to-analog converter (CDAC) synapse merges the input spikes and phase-frequency detector (PFD) outputs to generate the VCO control voltage. The neuron is implemented in a 28-nm CMOS technology and operates under a subthreshold supply voltage of 0.35 V. Occupying 154 μm2, measurement shows a maximum spike rate of 5.5 MHz and energy consumption of 159 fJ/spike.Keywords
Funding Information
- BYU’s Simmons Research Endowment
- National Science and Technology Council, Taiwan (NSTC 112-2221-E-A49-150, NSTC 112-2622-8-A49-013-SB)
- Higher Education Sprout Project of the National Yang Ming Chiao Tung University and Ministry of Education (MOE), Taiwan
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