Yen-Cheng Kuan

A W-band frequency-modulated continuous-wave (FMCW) radar, implemented in 65-nm CMOS, is proposed for intelligent transportation system (ITS) applications in this article. The system integrates four transmitters (TXs) and four receivers (RXs), along with a frequency synthesizer and a local oscillator (LO) distribution network. Both the low-noise amplifier (LNA) and the power amplifier (PA) adopt multistage cascaded topologies with magnetically coupled resonators (MCRs) to enable broadband operation. An ultrawideband class-B mixer, implemented with only an active switching core, supports continuous operation from 20 to 110 GHz. Furthermore, an LO distribution network featuring three cascaded frequency doublers achieves frequency octupling from an 11–13-GHz synthesizer, enabling wide-bandwidth (BW) modulation. Under the default configuration, the four TX and RX channels achieve a maximum TX output power of 13.4 dBm with 12.8% drain efficiency, an RX conversion gain (CG) of 64.4 dB, a minimum RX $\text {NF}_{\text {ssb}}$ of 8.4 dB, an RX in-band (IB) IP1dB from −49.4 to −43.6 dBm @3MHz offset, and an RX out-of-band (OOB) IP1dB from −17 to −11.1 dBm at 10-kHz offset across 90–98 GHz. The measured phase noise is −94.06 dBc/Hz at 1-MHz offset with a 90.4-GHz carrier. The root-mean-square (rms) error is 3.52 MHz (0.044%) for a sawtooth chirp with an 8-GHz range and a 20-MHz/ $\mu $ s chirp rate. Each TX/RX element consumes 208.5/76.5 mW, respectively, and the entire chip occupies a $4.5\times 3.8$ mm² area. To validate the radar operation, a slot substrate-integrated waveguide (SIW) antenna array, with a flip-chip chip-scale package (FCCSP) transceiver, is designed and fabricated on a Rogers 3003G2 PCB. The multiple-input–multiple-output (MIMO) radar prototype achieves a distance resolution of 2.85 cm and an angular resolution of 13° with a field of view (FOV) of 144°.

High-performance computing applications rely heavily on vector instructions to accelerate data processing. In this letter, we propose a controllable bitonic network (CBN) and use it as a lane interconnect to efficiently rearrange data across vector lanes of a vector processing unit to accelerate the execution of vector permutation instructions (VPIs). Our work focuses on the RISC-V vector instruction set because of its configurable vector length support. Through simulations with vector-permutation-intensive applications of a RISC-V vector benchmark suite (RiVEC), the proposed approach with an eight-lane 64-bit CBN demonstrates an average speedup of ≥6× regarding the VPI execution time over a conventional ring-network-based approach. In addition, to verify our approach on hardware, we implemented a processor system with an eight-lane 16-bit CBN on an AMD A7-100T FPGA operating at 20 MHz, demonstrating single-cycle execution of the RISC-V vr.gather and vr.scatter instructions.

This article presents a 27.731.2-GHz highly integrated eight-element, four-beam transmitter front end in 65-nm CMOS for phased-array multibeam communication. To eliminate beam interference in multibeam coherent communication, an interference cancellation scheme is introduced within the multibeam transmitter. In the circuit design, the proposed hybrid variable-gain amplifiers (VGAs) combine digital common-source (CS) VGAs and analog Gilbert-cell-based VGAs to achieve both a large dynamic range and high resolution. The hybrid VGAs are then embedded into a transmission-line-based network, forming a compact 4×4 beam combining structure. To support multibeam phase steering, four pairs of G_m arrays interpolate four individual phase sates from the same I/Q signals generated by low-and high-pass lumped delay lines. These delay lines are inserted between CS transistors and common-gate (CG) transistors to isolate the impedance fluctuates of magnetic coupling resonance load across frequency. To manage the high peak-to-average power ratio (PAPR) modulation signal, the output stage employs a symmetrical transformer-based Doherty load modulation network and an analog adaptive gain control in the auxiliary path to improve the power-back-off (PBO) efficiency. With a 1.1-V supply voltage, this transmitter achieves a saturated output power (P_sat) of 19.2 dBm with a 20.5% channel efficiency (CE) and an output power 1-dB compression point (OP_1dB) of 18.2 dBm. The measured maximum drain efficiency (DE) is 40.8%, while the 6-dB PBO DE is 28%, indicating improvements of 40%/180% compared to the normalized class-B/A implementations. The proposed hybrid VGA achieves a 27-dB tuning range and a 0.25-dB gain step with 0.26-dB/1.9^∘ root mean square (rms) gain/phase errors, while the phase shifter (PS) implements 6-bit, 360^∘ phase shifting with 0.25-dB/2.5^∘ rms gain/phase errors, enabling precise gain tapering and beam steering.

This paper proposes a RISC-V-based accelerator for inferring a model that uses Efficient Sparse Winograd Convolutional Neural Networks. This accelerator consists of a RISC-V processor (AndesNX27V) and a coprocessor; the latter performs the Winograd-ReLU convolutions and fully connected layers of the network. The pooling and ReLU layers of the network are executed by the processor in parallel with the coprocessor to increase throughput. In addition, on-chip buffers are used for the input/output data and filter weights to ensure pipelined operation. Implemented on an AMD VCU118 FPGA platform operating at 250 MHz, the accelerator achieves an average throughput of 5104.6 GOP/s when inferring a VGG16-based model.

This article presents a 17.720.2 GHz eight-element four-beam RF-beamforming transmitter in 65-nm CMOS for satellite communication (SATCOM). The transmitter utilizes an analog scheme in the variable-gain amplifier (VGA) to achieve dB-in-linear gain control with a high dynamic range (DR), together with a current combining crossbar for a compact footprint. The vector-modulation-based (VM-based) phase shifter (PS) adopts the cancellation-based $G_\mathrm{m}$ units for low switching variation. Furthermore, eight PSs of each beam are split into two groups, with each group sharing the same tunable I/Q generator for low power consumption. Considering the increased peak-to-average power ratio (PAPR) caused by high-order modulation schemes and multibeam operation, the transmitter incorporates compact transformer-based Doherty power amplifiers (DPAs) with adaptive bias control to improve the power efficiency at back-off. The chip achieves a 31-dB gain-tuning range with a 0.283-dB step and a 360 $^{\circ}$ phase-shifting range with a calibrated 7-bit resolution. The measured root-mean-square (RMS) phase/gain errors induced by the VGA/PS are below 2.05 $^{\circ}$ /0.147 dB, respectively, which decouples phase/gain control. The transmitter achieves a maximum output 1-dB gain compression point (OP $_{\mathrm{1 dB}}$ ) of 17.9 dBm and a maximum saturated power ( $P_{\mathrm{sat}}$ ) of 18.9 dBm. The output element exhibits 29.3% drain efficiency (DE) at 6-dB power back off (PBO) from $P_{\mathrm{sat}}$ , which is 1.56/3.12 times over the normalized class-B/class-A implementations, demonstrating Doherty PBO efficiency enhancement. The chip occupies an area of 8.59 $\times$ 4.17 mm $^2$ and consumes 398 mW per element at OP $_{\mathrm{1~dB}}$ . Additionally, a 16-element linear array has been developed to showcase the capabilities of the multibeam operation and gain tapering.

The multistage charge pump in a zero-crossing-based amplifier (ZCBA) presents complex tradeoffs. In this brief, we propose a generalized behavioral model for the ZCBA to quickly predict the optimal charge pump design for a ZCBA based on circuit parameters, without conducting time-consuming transistor-level simulations iteratively. This model enables us to numerically analyze in MATLAB the effects of the circuit parameters, which include the current scaling factor, the number of current sources, current value, and input amplitude, on the settling performance, including overshoot and settling time. The analysis results conclude that there exists an optimal number of stages that yields the fastest settling time for a given total current and load capacitance. Additionally, the settling time exhibits an asymptotic behavior with respect to the total current. To validate this behavioral model, we designed and simulated a transistor-level ZCBA in a 28-nm CMOS process, demonstrating a good agreement between the model analysis and simulation result.

The design and measurement of a time-domain analog spiking neuron is described. The proposed neuron leverages time-domain processing using voltage-controlled oscillators (VCOs) and a time-domain comparator to integrate the input spike and trigger the output spike. A novel leaky circuit uses a phase-locked loop (PLL) to drive the phase difference between the two VCOs toward zero. A weighted capacitive digital-to-analog converter (CDAC) synapse merges the input spikes and phase-frequency detector (PFD) outputs to generate the VCO control voltage. The neuron is implemented in a 28-nm CMOS technology and operates under a subthreshold supply voltage of 0.35 V. Occupying 154 μm2, measurement shows a maximum spike rate of 5.5 MHz and energy consumption of 159 fJ/spike.

A low-power 23–25.5-GHz frequency-modulated continuous wave (FMCW) radar transceiver, implemented in 65-nm CMOS, is proposed for artificial intelligence-Internet of Things (AIOT) applications in this article. The transceiver integrates a frequency synthesizer, a power amplifier (PA), a low noise amplifier (LNA), I/Q mixers, a quadrature all-pass filter (QAF)-based local oscillator (LO) generator, and an analog baseband (ABB). A current-sharing LNA using $g_m $ -boosting three-turn coupling transformers and an LO generator using injection locking technique are employed to render high gain with low power consumption. Furthermore, a Class-B mixer with bulk injection (BI) technique is proposed to alleviate LO signal strength requirement with low power while enhancing conversion gain (CG) and linearity. Measurements demonstrate that the transceiver demonstrates a peak transmitter (TX) output power of 12.6 dBm with 28.5% efficiency, a receiver (RX) CG of 54.2 dB, a minimum RX $\text{NF}_{\text{dsb}}$ of 5.7 dB @ 1.6-MHz offset, an RX IIP3 of $-$ 24 dBm and an RX IP1dB of $-$ 34.5 dBm @42-dB gain across 23–25.5 GHz from a 1-V supply. To further reduce power consumption, the transceiver can work under a low supply voltage of 0.75 V and can still deliver a 9.1-dBm TX output power with 19.2% efficiency, a 49.6-dB RX CG, a 7.9-dB RX $\text{NF}_{\text{dsb}}$ @1.6-MHz offset, a $-$ 29.1-dBm RX IIP3, and a $-$ 41.7-dBm RX IP1dB @ 42-dB gain across 23.2–24.8 GHz. The measured phase noise is $-$ 102 dBc/Hz at 1-MHz offset at 23.4 GHz. The root-mean-square (rms) frequency error is 120 kHz (0.12%) for a sawtooth chirp with 100-MHz bandwidth and 1-MHz/s chirp-rate. With two external 20-dBi horn antennas, the radar demonstrates a 15.6-cm range resolution with 960-MHz modulation bandwidth in 20-m indoor tests. The entire transceiver occupies a chip area of 2.3 $\times$ 3.7 mm $^{2}$ including pads and consumes 155.9 mW from a 1-V supply, and a 103.6 mW from a 0.75-V supply.

VCO-based ADCs widely utilize coarse-fine readout to save power and hardware compared to counter-only converters. However, the timing mismatch due to the clock skew between the coarse and fine quantizers can lead to significant reconstruction errors. This paper proposes a digital calibration circuit to detect and correct coarse-fine timing mismatch for VCO-based ADCs. The circuit includes overcount/undercount logic to detect all possible timing mismatch cases and generates a correction value to digitally remove the errors. The calibration operates continuously in the background and is entirely digital, making it scaling-friendly and robust against analog imperfections. Simulations show that a VCO-based ADC utilizing the calibration circuit improves the SNR by 10.3 dB and 6.9 dB versus a conventional coarse-fine converter and one with a conventional retiming calibration, respectively.

This work presents the design, creation, and testing of ultrawideband millimeter-wave (mmWave) antennas with a tightly coupled array (TCA) configuration. These antennas are made using metamaterial (MTM) designs and advanced high-density interconnect (HDI) antenna-in-package (AiP) technologies, ideal for beyond-5G (B5G) and 6G networks. The main elements of the MTM antenna array are constructed with silicon-based integrated passive device (IPD) technology and are flip-chip bonded to a multi-layered HDI-PCB that includes a resistive frequency selective surface (FSS). These array antennas are differentially fed through a coax-via system. The study presents two types of 5×5 finite arrays: a metal-insulator-metal (MIM) capacitor-based MTM bowtie array with a differential Voltage Standing Wave Ratio (VSWR) ≤ 3.5, operating from 16.2 to 100 GHz (excluding 18.26 – 18.68 GHz and 60.8 – 61.13 GHz), and an interdigital capacitor-based MTM bowtie array functioning from 18.85 to 100 GHz (excluding 41.52 – 42.25 GHz). Experimental validation of these prototypes confirms their performance, aligning well with simulated results in terms of bandwidth and radiation characteristics.