Double-Layer-Stacked Silicon Interposer for 2.5-D Packaging of 32 × 32 Micromirror Array Chip

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Abstract
Aimed at packaging our previously-developed bulk-silicon-micromachined 32×32 micromirror array (MMA) chip (33×34×0.4mm3 in dimension and 4114 pads) while minimizing coefficient of thermal expansion (CTE) mismatch, this paper, for the first time, develops a double-layer-stacked silicon interposer (DLSSI), which is 49.8×49.8×0.387mm3 in dimension and has 8 redistribution layers (RDLs). It is realized by fabricating two single-layered silicon interposers (SLSIs) with 175μm-thickness core layer and 4 RDLs equally arranged on both sides, and then adopting Cu-Sn bonding to integrate them together. Such design improves the thickness and the number of RDLs of silicon interposer. Thus, the DLSSI not only has higher structural strength for guaranteeing itself to go through packaging process intactly, but also has higher routing capability for numerous and complicated electric interconnections. Herein, the total quantity of electrical interconnections in the DLSSI is 8336. A dimension-by-dimension fan-out strategy is proposed, which successfully maps pads of the 32×32 MMA chip to their corresponding pads of high voltage ASICs (HV-ASICs) in 4 RDLs (the rest 4 RDLs are for powers, reference voltages and control signals of the HV-ASICs). The equivalent CTE of the DLSSI is calculated to be 3.5ppm/℃, and the theoretical warpage of the 32×32 MMA chip after the packaging process is calculated to be about 3μm with full-scale finite element analysis (FEA). Besides, the warpage and conductance yield of the DLSSI are measured experimentally. Based on the DLSSI, a vertically integrated 32×32 MMA module that includes a PCB connector, 16 HV-ASICs and 80 capacitors is developed successfully.
Funding Information
  • Shanghai Sailing Program (No. 20YF1456600)

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