Verification-Guided Soft Error Resilience
- 1 April 2007
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 15301591,p. 1-6
Abstract
Algorithmic techniques for formal verification can be used not just for bug-finding, but also to estimate vulnerability to reliability problems and to reduce overheads of circuit mechanisms for error resilience. We demonstrate this idea of verification-guided error resilience in the context of soft errors in latches. We show how model checking can be used to identify latches in a circuit that must be protected in order that the circuit satisfies a formal specification. Experimental results on a Verilog implementation of the ESA SpaceWire communication protocol indicate that the power overhead of soft error protection can be reduced by a factor of 4.35 by using our approach rather than protecting all latchesKeywords
This publication has 13 references indexed in Scilit:
- Sequential Element Design With Built-In Soft Error ResilienceIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006
- Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods2006
- Design for soft error mitigationIEEE Transactions on Device and Materials Reliability, 2005
- Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices2005
- Logic soft errors in sub-65nm technologies design and CAD challenges2005
- Characterizing the effects of transient faults on a high-performance processor pipeline2004
- Coverage estimation for symbolic model checking2003
- A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor2003
- Fault injection techniques and toolsComputer, 1997
- FERRARI: a flexible software-based fault and error injection systemIEEE Transactions on Computers, 1995