Theoretical Study for Carrier Transit Limited Performance of Gate-All-Around Si Nanowire Transistor by Time-Dependent Quantum Transport Simulation

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Abstract
Theoretically, the upper limit performance of nanoscale transistor should be limited by carrier transit time through the channel as the charge in channel cannot follow the gate voltage and the gate capacitance will show strong frequency dependence if the gate voltage varies faster than the carrier transit time. Currently, the operation frequency of nanoscale transistor is limited by the non-ideal factors such as parasitic effects, and it is far below the limit caused by carrier transit time. However, how good the transistor can be if one can minimize these non-ideal factors is still a problem, thus, it would be worth exploring its upper limit performance. In this article, time-dependent quantum transport simulation is performed to explore the carrier transit limited performance of the gate-all-around (GAA) Si nanowire transistor. By using the mode space approach, the 3-D time-dependent quantum transport equation is decoupled to a 2-D confinement problem and a 1-D transport problem, and then self-consistently solved with the Poisson’s equation. The transient characteristics of channel charge are investigated, and it shows the response time of channel charge is in the scale of 0.1 ps. The responses of channel charge and drain current to high-frequency gate voltages are simulated. The carrier transit limited performance including the frequency-dependent gate capacitance and transconductance, 3 dB bandwidth, and cutoff frequency, are calculated and discussed.
Funding Information
  • National Natural Science Foundation of China (62122067, 61971375, 62071424)
  • Zhejiang Provincial Natural Science Foundation (LR21F010003, LD21F010002)

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