Junction Temperature-Based Adaptive Short Circuit Detection Technique for SiC MOSFETs
- 21 April 2026
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Industrial Electronics
- Vol. PP (02780046) , 1-12
Abstract
Silicon carbide (SiC) MOSFETs have a low short-circuit (SC) withstand capacity. Hence, an SC detection circuit with a low SC detection time ($\boldsymbol{t}_\boldsymbol{SCD}$) and high robustness is required to achieve an effective SC protection for SiC MOSFETs. To achieve both the objectives simultaneously, mostly two-stage SC detection techniques are suggested in the literature. The primary stage in these techniques is designed to have a very low $\boldsymbol{t}_\boldsymbol{SCD}$. However, a few of the suggested primary stage are known to have a low robustness while the others are known to be incapable of detecting a fault under load (FUL) SC condition. To improve the overall robustness and to identify FUL, a desaturation (DESAT)-based SC detection technique is usually used as a secondary stage. In a DESAT-based technique, the reference voltage ($\boldsymbol{V}_\mathbf{REF}$) for SC detection is kept based on the power device output characteristic and its worst-case operating junction temperature ($\boldsymbol{T}_\boldsymbol{J}$). However, this leads to a suboptimal $\boldsymbol{t}_\boldsymbol{SCD}$ as the device may not be operating at its worst-case $\boldsymbol{T}_\boldsymbol{J}$ preceeding an SC event. Thereby, this may adversely affect the SC protection effectiveness by making the secondary stage slower. To address the aforementioned challenge, this manuscript proposes a novel technique to adaptively vary $\boldsymbol{V}_\boldsymbol{REF}$ based on the feedback of $\boldsymbol{T}_\boldsymbol{J}$ to achieve an optimal $\boldsymbol{t}_\boldsymbol{SCD}$. Further, the mathematical formulation for the rate at which $\boldsymbol{V}_\boldsymbol{REF}$ should be varied and operational constraints necessary to mitigate a misdetection during normal operation are also determined. Experimental investigation of the proposed technique is carried out by conducting SC at 800 V on a 1.2 kV rated SiC MOSFET. Results show up to 24.3% reduction in $\boldsymbol{t}_\boldsymbol{SCD}$ compared with the existing secondary protection technique.Keywords
Funding Information
- Indian Institute of Technology Bombay
- Department of Science and Technology
- The IIT Bombay-Ohio State Frontier Science and Engineering Research Centre
- Prime Minister’s Research Fellowship (PMRF) Scheme
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