A CGRA frontend for bandwidth utilization in HiPReP

This publication has 16 references indexed in Scilit:

• A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective
  IEEE Access, 2020
• Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
  IEEE Micro, 2020
• Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores
  IEEE Transactions on Computers, 2020
• DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing
  IEEE Micro, 2012
• Memory bandwidth optimization through stream descriptors
  ACM SIGARCH Computer Architecture News, 2005
• The AMIDAR Class of Reconfigurable Processors
  The Journal of Supercomputing, 2005
• Architecture Exploration for a Reconfigurable Architecture Template
  IEEE Design & Test of Computers, 2005
• Some Computer Organizations and Their Effectiveness
  IEEE Transactions on Computers, 1972
• Validity of the single processor approach to achieving large scale computing capabilities
  1967
• Very high-speed computing systems
  Proceedings of the IEEE, 1966