Christian Hochberger

Memristor-based configuration memory offers an alternative solution to the volatility and large area overhead of conventional Static Random Access Memory (SRAM)-based FPGA configuration memory. Their non-volatile nature and the possibility of stacking them on top of the logic layer in a process called Back-End-Of-Line (BEOL) manufacturing help not only dramatically reduce area consumption but also significantly reduce startup time. However, due to the comparatively high defect probability caused by manufacturing defects, traditional approaches for defect tolerance are not fit to address these defects. This work introduces an approach to defect-aware and tolerant synthesis. Based on this, an investigation into the defect tolerance of different architecture choices regarding the size of LUTs and the fracturability of LUTs is presented. We can show that smaller, non-fracturable LUTs exhibit a higher defect tolerance. Moreover, multiple strategies to improve the mapping result based on the properties of the logic functions are introduced. Notably, reducing the mapping complexity of logic clusters during the packing stage significantly improves the mapping success rate.

As with any memory device, programming a memristor involves trade-offs between power, energy, and time. In this letter, we investigate in detail how these factors are interrelated under different programming conditions. We show that, under time constraints, lower energy consumption can be achieved using faster programming pulses at the cost of increased power dissipation. Conversely, when limiting the maximum power is the priority, longer programming times are required to minimize energy consumption. These trade-offs ultimately stem from the physical response time of ions and vacancies involved in the formation and dissolution of the conductive filament within the oxide layer of a metal-insulator-metal (MIM) structure. We begin by analytically examining the effect of applying a single trapezoidal pulse to the device. Next, we extend the analysis to multiple pulses, using a compact recursive approach to model both potentiation and depression. Finally, we perform SPICE simulations under unconstrained programming conditions. Modeling and simulations are based on the Dynamic Memdiode Model, combined with the Method of Elementary Solvers. Given the variability of device parameters and experimental conditions, we provide the complete SPICE schematic to allow interested readers to explore different scenarios and tailor the analysis to their specific use cases.

This work investigates the spectral and energetic aspects of memristor programming using generalized Gaussian voltage pulses. Unlike conventional square or triangular waveforms, generalized Gaussian pulses enable precise control over both temporal shape and frequency content through a tunable shape parameter. By systematically varying the pulse’s effective width and sharpness, we analyze the resulting current response and its dependence on the memristor’s nonlinear and memory-driven dynamics. SPICE simulations reveal how pulse shaping directly affects the spectral distribution, instantaneous power consumption, total programming energy, and programming time. The results highlight key trade-offs among frequency-domain characteristics, pulse amplitude, and energy efficiency, providing practical design guidelines for energy-aware memristive programming. Controlling the frequency spectrum in memristive circuits is critical to preventing parasitic elements in wires and devices from introducing additional signal distortion, which could compromise the accuracy and reliability of in-memory operations. These findings have potential implications for low-power neuromorphic computing, analog signal modulation, and waveform-optimized memory architectures.

Energy and its dissipation are fundamental to all living systems, including cells. Insufficient abundance of energy carriers─as caused by the additional burden of artificial genetic circuits─shifts a cell's priority to survival, also impairing the functionality of the genetic circuit. Moreover, recent works have shown the importance of energy expenditure in information transmission. Despite living organisms being non-equilibrium systems, non-equilibrium models capable of accounting for energy dissipation and non-equilibrium response curves are not yet employed in genetic design automation (GDA) software. To this end, we introduce Energy Aware Technology Mapping, the automated design of genetic logic circuits with respect to energy efficiency and functionality. The basis for this is an energy aware non-equilibrium steady state model of gene expression, capturing characteristics like energy dissipation─which we link to the entropy production rate─and transcriptional bursting, relevant to eukaryotes as well as prokaryotes. Our evaluation shows that a genetic logic circuit's functional performance and energy efficiency are disjoint optimization goals. For our benchmark, energy efficiency improves by 37.2% on average when comparing to functionally optimized variants. We discover a linear increase in energy expenditure and overall protein expression with the circuit size, where Energy Aware Technology Mapping allows for designing genetic logic circuits with the energetic costs of circuits that are one to two gates smaller. Structural variants improve this further, while results show the Pareto dominance among structures of a single Boolean function. By incorporating energy demand into the design, Energy Aware Technology Mapping enables energy efficiency by design. This extends current GDA tools and complements approaches coping with burden in vivo.

Deep neural networks (DNNs) are a type of artificial intelligence models that are inspired by the structure and function of the human brain, designed to process and learn from large amounts of data, making them particularly well-suited for tasks such as image and speech recognition. However, applications of DNNs are experiencing emerging growth due to the deployment of specialized accelerators such as the Google’s Tensor Processing Units (TPUs). In large-scale deployments, the energy efficiency of such accelerators may become a critical concern. In the voltage overscaling (VOS) technique, the operating voltage of the system is scaled down beyond the nominal operating voltage, which increases the energy efficiency and lifetime of digital circuits. The VOS technique is usually performed without changing the frequency resulting in timing errors. However, some applications such as multimedia processing, including DNNs, have intrinsic resilience against errors and noise. In this paper, we exploit the inherent resilience of DNNs to propose a quality-aware voltage overscaling framework for TPUs, named X-TPU, which offers higher energy efficiency and lifetime compared to conventional TPUs. The X-TPU framework is composed of two main parts, a modified TPU architecture that supports a runtime voltage overscaling, and a statistical error modeling-based algorithm to determine the voltage of neurons such that the output quality is retained above a given user-defined quality threshold. We synthesized a single-neuron architecture using a 15-nm FinFET technology under various operating voltage levels. Then, we extracted different statistical error models for a neuron corresponding to those voltage levels. Using these models and the proposed algorithm, we determined the appropriate voltage of each neuron (the voltage level of each column of the X-TPU). Results show that running a DNN on X-TPU can achieve 32% energy saving for only 0.6% accuracy loss.

Energy and its dissipation are fundamental to all living systems, including cells. Insufficient abundance of energy carriers -as caused by the additional burden of artificial genetic circuits-shifts a cell’s priority to survival, also impairing the functionality of the genetic circuit. Moreover, recent works have shown the importance of energy expenditure in information transmission. Despite living organisms being non-equilibrium systems, non-equilibrium models capable of accounting for energy dissipation and non-equilibrium response curves are not yet employed in genetic design automation (GDA) software. To this end, we introduce Energy Aware Technology Mapping, the automated design of genetic logic circuits with respect to energy efficiency and functionality. The basis for this is an energy aware non-equilibrium steady state (NESS) model of gene expression, capturing characteristics like energy dissipation -which we link to the entropy production rate- and transcriptional bursting, relevant to eukaryotes as well as prokaryotes. Our evaluation shows that a genetic logic circuit’s functional performance and energy efficiency are disjoint optimization goals. For our benchmark, energy efficiency improves by 37.2% on average when comparing to functionally optimized variants. We discover a linear increase in energy expenditure and overall protein expression with the circuit size, where Energy Aware Technology Mapping allows for designing genetic logic circuits with the energy efficiency of circuits that are one to two gates smaller. Structural variants improve this further, while results show the Pareto dominance among structures of a single Boolean function. By incorporating energy demand into the design, Energy Aware Technology Mapping enables energy efficiency by design. This extends current GDA tools and complements approaches coping with burden in vivo . TOC Graphic:

Tuning the conductance of a memristive device is a process that requires energy and involves power dissipation. In this letter, the role the memory state programming strategy plays in this connection is investigated. To this end, the device model equations representing the electron transport and metal ion/oxygen vacancy displacement caused by the application of an external signal must be solved consistently. However, if instead of considering the applied voltage as the model input, a memory state trajectory is assumed, the model equations can be decoupled allowing an analytic description of the problem. In order to accomplish this objective a more accurate version of the dynamic memdiode model is used which incorporates additional physical considerations in the characteristic switching times. It is demonstrated that alternative trajectories (concave, convex, and sigmoidal) lead to a variety of energy consumption-maximum dissipated power relationships highlighting the key role played by the selected programming strategy. This kind of study contributes to the basic understanding of the writing process of memristors (synaptic weight assignment in neural networks) shedding light on the associated electrical effects.