Abstract
This paper presents an ultra-low quiescent current output-capacitorless low dropout regulator (OCL-LDO) with fast transient response. We design a rail-to-rail error amplifier with improved adaptive biasing, which provides a limited bias current at heavy load for better load regulation. The buffer with adaptive biasing and almost zero input-output voltage shift and embedded body-bias, combines the error amplifier and the gate of M P . The proposed LDO is designed in a 65-nm CMOS process. Simulation result shows that the proposed LDO consumes a quiescent current of only 23 nA at a supply voltage of 0.8 V. The voltage undershoot is 98 mV during a 20-mA maximum load transient. And we obtain a FOM T of 0.00023 ps.
Funding Information
  • National Natural Science Foundation of China
  • Technology Development

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