Xiangyu Mao

In audio and imaging applications, signals are highly sensitive to power supply noise, and the load conditions can change frequently during the signal processing. Therefore, it is essential to utilize a low-dropout regulator (LDO) with high power supply rejection (PSR) across the wide load range. This brief presents an LDO with an adaptive feed-forward-capacitor array that can track the load current and input voltage variations to realize near-optimum feed-forward ratio, for improving PSR in all designed operating conditions. The proposed LDO is fabricated in a 180 nm CMOS process. Measurement results show that the proposed LDO achieves better than $-$60 dB PSR over 1–180 mA load current and 1.8–2.4 V input voltage range, with an output of 1.6 V. And the proposed adaptive technique only uses a total of 5.9 pF additional on-chip capacitor.

The development of fast charging technology has significantly reduced the charging time for devices. However, with the increase of power level, the thermal and size issues become the limiting factors for fast charging, especially for compact devices. This article presents the concept of the voltage-regulating cable (VRC) which integrates the charging IC and all the associated passive components into the universal serial bus (USB) cable connector. By relocating the power converter and its associated heat from the devices to the cable, this design significantly reduces the device size and provides an alternative solution for the overheating issues. The VRC can regulate a bidirectional step-down voltage for two kinds of typical application scenarios: adapter-to-device (A2D) and device-to-device (D2D) scenarios. In addition, a symmetrical VRC structure is also proposed to facilitate a reversible and user-friendly connection. The designed VRC prototype, fabricated in 180-nm high-voltage BCD process, occupies an area of 4.7 × 2.9 mm², including all passive components. It achieves a peak power density of 3.17 W/mm² when transferring the maximum power of 42 W in the A2D scenario and a peak power density of 1.36 W/mm² with a maximum power of 18 W in the D2D scenario.

Energy-efficient compact smart devices operate at a supply voltage as low as 0.5 V, powered by either a battery (3–4.2 V) or a universal serial bus (USB) port (5 V), demanding a voltage conversion ratio (VCR) as large as 10:1. This work proposes a multi-path inductor-first inductor-on-ground switched-capacitor (L $^{{2}}$ SC) hybrid buck dc–dc converter for large VCR and high-power density. The inductors on the input and the ground nodes combine and reuse the parasitic inductors from PCB routing and bonding wire, enable a continuous input current, and relieve the electromagnetic interference (EMI) issue. In addition, the two inductors in this converter operate in an interleaved fashion, obtaining reduced output current ripple. The SC network reduces the average inductor current and enlarges the output capability. This work, fabricated in a 180-nm BCD process, uses only 2-V NMOS power transistors, withstanding 3–5-V input and delivering 0.5–1.2-V output. This work achieves a peak efficiency of 96.1% with a high chip-area current density of 1.02 A/mm $^{{2}}$ .

Distributed low-dropout voltage regulators (LDOs) can mitigate the global IR drop and improve the local transient performances for a high-current large-area power delivery network. However, they also face integration and current-sharing challenges. To tackle these challenges, this article presents an all-digital dual-loop distributed LDO with one global controller (GC) and multiple scalable local voltage regulators (LVRs). For fully synthesizable and easy integration, all the control circuits are implemented using standard digital cells. In each LVR, we use a 5-bit time-to-digital converter (TDC) for fast local voltage sensing. The global integral loop provides the dynamic reference bits for all the LVRs, compensating the TDC PVT variations in the LVRs. This all-digital comparator-TDC quantizer, combined with coarse-fine tuning and asynchronous window control, enables the proposed LDO architecture to obtain high output accuracy and one-cycle transient response. For current balancing in distributed scenarios, we introduce a digital primary-secondary one-time calibration scheme to tackle the mismatches among the local TDCs. A distributed LDO prototype with one GC and nine LVRs is implemented in a 28-nm bulk CMOS process. Measurements with one LVR and multiple LVRs demonstrate the stability and scalability of the proposed architecture. With nine LVRs, the measured droop is 54 mV under a 1.35-A/10-ns sharp load step. We also obtain a good load regulation of 3 mV/A, a peak current efficiency of 99.67%, and a current density of 16.7 A/mm $^{{2}}$ .

This paper presents an ultra-low quiescent current output-capacitorless low dropout regulator (OCL-LDO) with fast transient response. We design a rail-to-rail error amplifier with improved adaptive biasing, which provides a limited bias current at heavy load for better load regulation. The buffer with adaptive biasing and almost zero input-output voltage shift and embedded body-bias, combines the error amplifier and the gate of M P . The proposed LDO is designed in a 65-nm CMOS process. Simulation result shows that the proposed LDO consumes a quiescent current of only 23 nA at a supply voltage of 0.8 V. The voltage undershoot is 98 mV during a 20-mA maximum load transient. And we obtain a FOM T of 0.00023 ps.

Parallel connected low-dropout regulators (LDOs) are commonly used to share the large load current in communication baseband systems. This paper presents a PCB-friendly, reconfigurable master-slave parallel LDO scheme with analog regulation and digital distribution, to deliver Ampere-level load current with small current mismatches. The proposed LDO adopts a series analog-digital merged control, where the first loop is a high-gain analog error amplifier for high-accuracy regulation, and the second loop utilizes a 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) for the tradeoffs between resolution, energy-efficiency, and fast response. Each LDO can be configured into the master or slave mode. When multiple LDOs are connected in parallel, the master LDO also controls the digital power cells in the slave LDOs. By employing an auxiliary constant current control, the power cells in each LDOs work as a constant current source array. The same control code naturally enables the output current balancing among each LDOs. Fabricated in 65-nm CMOS, the proposed LDO obtains an excellent load regulation of $<$ 1.5mV/A across the full load range of 0-1A, with 99.9% peak current efficiency. For four parallel LDOs with each delivering 1-A load current, the measured current-sharing mismatch is only $<$ 0.76% with no additional external components.

This brief presents a 1-A fully-integrated switching LDO for digital loads. By using 4-phase 200-MHz pulse-width modulation (PWM), it can significantly reduce the output ripple and allow using a smaller output capacitor. Distinctive from the prior dual-loop structure, we adopt a single feedback loop with a wide bandwidth error amplifier (EA) using a quasi-Type-III compensation to improve the dynamic voltage scaling (DVS) rate and to reduce the transient recovery time. Meanwhile, compared with the prior stacked power transistor architecture, the single-PMOS with auxiliary constant current (ACC) control can reduce by 4-fold the power transistor size, and decreases the driver current by at least 2.5 times. Fabricated in 28-nm bulk CMOS, the proposed LDO measures a 1-A load capability with a 40-mV dropout voltage. Moreover, the measured load regulation is 2.2 mV/A, and the line regulation is 1.8 mV/V. In addition, the regulator obtains a fast DVS speed of 4V/μs and a fast load transient recovery time of <50ns.

This paper presents a high-current calibration-free analog-digital hybrid controlled LDO for large-area digital load. The proposed architecture has the advantages of an analog controller (continuous and high DC accuracy) with distributed digital power transistors (flexible and scalable for high current applications). Distinctive from the conventional digital LDOs that directly quantize the output voltage, the proposed LDO utilizes an error amplifier (EA) to pre-amplify the $\text{V}_{\mathrm {OUT}}$ error. Then, a 5-bit time-to-digital converter (TDC) quantizes the processed analog error signal subsequently transformed into a thermometer code that directly controls the distributed digital power transistors. This design can pull off high DC accuracy even without calibration. Besides, we implement an auxiliary constant current (ACC) circuit to solve reliability issues and to improve the stability under a large voltage dropout. Fabricated in a 28-nm bulk CMOS process with a 1.2-A load capability, the proposed LDO achieves 2- $\mu \text{V}$ /mA load regulation and close to 1.5% output accuracy. By employing a wide bandwidth EA and a fast TDC, the hybrid LDO can obtain a fast transient response. The measured undershoot is 70 mV with a 0.6-A load step within 10-ns edge time, and the output voltage can scale from 0.6 V to 0.9 V within 30 ns.