A Quarter-Rate Forwarded Clock Receiver Based on ILO With Low Jitter Tracking Bandwidth Variation Using Phase Shifting Phenomenon in 65 nm CMOS
Authors:
- 8 July 2014
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 61 (8) , 2482-2490
Abstract
This paper presents a quarter-rate forwarded clock (FC) receiver based on an injection-locked oscillator (ILO) which exploits a phenomenon in which phases of the output clock are shifted by the duty-cycle of an injection clock. Also, this paper describes the principle of this phase shifting phenomenon. To utilize the phase shifting phenomenon, a simple duty-cycle adjuster (DCA) is proposed. By using the DCA, the proposed FC receiver achieves 760 MHz of wide jitter tracking bandwidth (JTB) and 60 MHz JTB variation in spite of clock deskew. The proposed receiver achieves a 12 Gb/s data rate with 0.92 mW/Gb/s in a 1 V 65 nm CMOS process.Keywords
Funding Information
- Basic Science Research Program
- MEST
- IC Design Education Center (IDEC)
This publication has 8 references indexed in Scilit:
- 7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOSIEEE Journal of Solid-State Circuits, 2011
- A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOSIEEE Journal of Solid-State Circuits, 2010
- Strong Injection Locking in Low-$Q$ LC Oscillators: Modeling and Application in a Forwarded-Clock I/O ReceiverIEEE Transactions on Circuits and Systems I: Regular Papers, 2009
- Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A TutorialIEEE Transactions on Circuits and Systems I: Regular Papers, 2009
- A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOSIEEE Journal of Solid-State Circuits, 2008
- A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOSIEEE Journal of Solid-State Circuits, 2007
- A second-order semidigital clock recovery circuit based on injection lockingIEEE Journal of Solid-State Circuits, 2003
- A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architectureIEEE Journal of Solid-State Circuits, 2001