Noise modeling for RF CMOS circuit simulation
Authors:
- A.J. ScholtenASA.J. Scholten
- R. van LangeveldeRLR. van Langevelde
- V.C. VeneziaVVV.C. Venezia
Top Cited Papers
- 5 June 2003
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 50 (3) , 618-632
Abstract
The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.Keywords
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