A 800 MHz Fully Synthesizable PLL with Calibration-Free Feedforward Noise Cancellation
Authors:
- 15 May 2023
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
Abstract
SummaryA novel calibration-free feedforward noise cancellation (FNC) scheme for cell-based synthesizable all-digital phase locked loop (ADPLL) is presented. FNC is realized by selecting the ring-oscillator (RO) phase closest to the reference edge as the output clock on each reference cycle. We present an analytical model for FNC performance based on the frequency domain analysis on different noise sources. Fabricated in 65nm 1.2-V CMOS technology, the cell-based ADPLL layout is done by an automatic place and route (APR) tool except for the 2 auxiliary cells comprising the DCO. Measurement results show that the novel feedforward scheme suppresses in-band phase noise by 15 dBc/Hz, and integrated rms jitter by 4.22x with only 0.25mW of additional power consumption when the contribution of DCO random noise dominates TDC quantization noise. However, on the opposite case (TDC noise > DCO noise), the feed-forward scheme increases the out-of-band noise and rms jitter. The frequency domain analytical model predicts this tendency of the measurement results. We propose a condition for the feed forward scheme to be beneficial based on the analytical model and simulation results.Keywords
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