System-Technology Codesign of 3-D NAND Flash-Based Compute-in-Memory Inference Engine

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Abstract
Owing to its ultra-high density and commercially matured fabrication technology, 3D NAND Flash memory has been proposed as an attractive candidate of inference engine for deep neural network (DNN) workloads. However, the peripheral circuits require to be modified with conventional 3D NAND Flash to enable compute-in-memory (CIM) and the chip architectures need to be redesigned for an optimized dataflow. In this work, we present a design of 3D NAND-CIM accelerator based on the macro parameters from an industry-grade prototype chip. The DNN inference performance is evaluated using the DNN+NeuroSim framework. To exploit the ultra-high density of 3D NAND Flash, both inputs and weights mapping strategies are introduced to improve the throughput. The benchmarking on VGG network was performed across the technological candidates for CIM including SRAM, RRAM and 3D NAND. Compared to the similar designs with SRAM or RRAM, the result shows that 3D NAND based CIM design can achieve not only 17-24% chip size but also 1.9-2.7 times more competitive energy efficiency for 8-bit precision inference. Inference accuracy drop induced by 3D NAND string current drift and variation is also investigated. No accuracy degradation by current variation was observed with the proposed input mapping scheme while accuracy drops sensitive to the current drift, which implies some compensation schemes are needed to maintain the inference accuracy.

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