CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling
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- 19 January 2023
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 70 (3) , 883-890
Abstract
This article explores and evaluates six-transistor static random access memory (SRAM) bitcell design options for sequential and monolithic complementary field-effect transistors (CFET) in 5-Å-compatible (A5) and 3-Å-compatible (A3) technology. A5 CFET offers up to 55% and 40% SRAM bitcell area scaling due to stacked architecture as compared to 14-Å-compatible (A14) nanosheet (NS) technology and 10-Å-compatible (A10) forksheet (FS) technology counterparts, respectively. A dielectric isolation wall (DIW) between gates is introduced in A3 CFET SRAM as a scaling booster. Replacement of gate-cuts with DIW results in up to 17% bitcell area scaling in A3 as compared to A5 CFET SRAM. However, aggressive area scaling introduces routing complexity and limits the node-to-node power and performance (PP) gain. Thus, the interconnect design guidelines are provided to overcome these challenges for power, performance, and area (PPA) enhancements of high-density (HD) SRAM.Keywords
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