Shairfe Muhammad Salahuddin

In sub 10 nm nodes, the growing dominance of interconnects in chips poses challenges in designing large-size static random-access memory (SRAM) subarrays. The main issue is the write failure problem arising from the increased resistance and capacitance for bitline (BL) and wordline (WL). To tackle this issue, the SRAM subarray design incorporates conventional (Conv.) divided WL and divided BL techniques based on 14-Å-compatible (A14) nanosheet (NS) technology. This approach allows for various subarray sizes with successful write operations, resulting in improved subarray-level performance and power (PP). However, the additional logic gates come with an area penalty that may degrade the overall performance, power, and area (PPA) at the macro level due to increased inter-subarray interconnect overhead. To overcome this limitation, the active interconnect (AIC) design is proposed with the features of fabricating another or multiple active regions at the back-end of line (BEOL) layers. By moving these extra logic gates from front-end of line to BEOL in the AIC divided subarray design, the area penalty is significantly mitigated without compromising PP compared to the standard (Std.) and Conv. divided counterparts. To achieve this concept, carbon nanotube gate-all-around transistor is explored as potential BEOL-compatible device. In this research, a comprehensive design-technology co-optimization analysis is conducted to verify the value and potential benefits of up to 65% macro-level energy-delay-area product improvement by AIC divided subarray design compared to the Std. subarray design.

In this paper, we introduce a novel design of a 3D static random-access memory (SRAM) macro in a 3D Nanofabric process technology. The 3D Nanofabric technology is based on enabling the processing of N stack of identical layers simultaneously regardless of the number of stacked layers which consequently reduces the fabrication cost as well as the footprint of SRAM macros. To enable simultaneous patterning of stacked layers, 3D Nanofabric requires circuit topology and layout that rely on a single layer where the device channel, poly, and metal wires are all embedded without any other crossing than the gate on top of the device channel. Accordingly, we modify the layouts of the conventional SRAM bit-cell and periphery circuits which are complex and contain several metal crossings. Furthermore, we propose a new overall organization of the 3D SRAM macro that incorporates a stack of multiple identical layers each consisting of an equal size 2D array of bit-cells and the periphery circuits. We show that the proposed 3D Nanofabric SRAM macro offers 71.2% footprint gain and 36.3% read access speed improvement compared to equal size 2D SRAM macro in 3 nm FinFET.

This article explores and evaluates six-transistor static random access memory (SRAM) bitcell design options for sequential and monolithic complementary field-effect transistors (CFET) in 5-Å-compatible (A5) and 3-Å-compatible (A3) technology. A5 CFET offers up to 55% and 40% SRAM bitcell area scaling due to stacked architecture as compared to 14-Å-compatible (A14) nanosheet (NS) technology and 10-Å-compatible (A10) forksheet (FS) technology counterparts, respectively. A dielectric isolation wall (DIW) between gates is introduced in A3 CFET SRAM as a scaling booster. Replacement of gate-cuts with DIW results in up to 17% bitcell area scaling in A3 as compared to A5 CFET SRAM. However, aggressive area scaling introduces routing complexity and limits the node-to-node power and performance (PP) gain. Thus, the interconnect design guidelines are provided to overcome these challenges for power, performance, and area (PPA) enhancements of high-density (HD) SRAM.

An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed in this article. Increased bitline (BL) resistance in sub-10 nm node has hindered BL from fully discharge during a write operation. Furthermore, the write ability is degraded by an increased leakage current of half-selected bitcells on BL and BL capacitance operated in high frequency. In a realistic write operation, BL parasitics also cause 30% SRAM yield loss in interconnect resistance-dominated technology nodes. Thus, this proposed method analyzes the time-dependent impacts of BL parasitic resistors, capacitors, and pass-gate (PG) transistors on write margin considering the negative BL (NBL) assist technique.

The metal resistance increase due to interconnect pitch scaling was traditionally offset by interconnect length scaling. This is no longer the case for deeply scaled nodes with narrow critical dimensions (CDs) of metals. Static random access memories (SRAMs) route long critical signals such as bitlines and wordlines in lower metal layers of the back-end-of-line (BEOL) and are particularly affected by this metal resistance increase. Buried power rail (BPR) has been proposed in sub-5-nm nodes for routing power and ground lines to improve the performance and density of standard cells and mitigate voltage IR drop issues. We extend the work by exploring the use of buried interconnect for both signal and power routing in SRAMs with minimal process flow changes to the already proposed BPR technology. A high-accuracy 3-D field solver is used for accurate parasitic extraction of SRAM bitcells with buried interconnects. Industry-standard methods are used to evaluate the SRAM macro-level power-performance metrics. We show that the buried interconnects can improve SRAM access time by up to 11%, write time by up to 28%, and dynamic power by 4%, effectively equivalent to one full technology-node gain improvement.

This article explores the feasibility of high-temperature annealing for top-tier devices in a sequential 3-D (Seq3D) technology. Thermally stable bottom-tier device and interconnect design guidelines are provided. CMOS-SRAM partitioning is proposed to achieve performance gain from Seq3-D. The implications of thermally stable Seq3-D on system-level performance are evaluated. Seq3-D wafer and die cost of ownership are estimated.

This letter proposes for the first time buried powered Static Random-Access Memory (SRAM) to achieve enhanced write margin and performance in advanced CMOS technology nodes. The buried power rail (BPR) for SRAM is silicon verified. The BPR helps to lower the bitline and wordline resistance by relaxing metal width in SRAM circuits and thereby enhances the write margin and performance. The proposed SRAM provides up to 340mV and 30.6% improvement in write margin and read speed, respectively, as compared to its conventional counterpart without incurring any area penalty in a hardware influenced 3nm CMOS technology.

A new single-ended read asymmetrical SRAM cell with underlap engineered symmetrical FinFETs is proposed in this paper for achieving stronger data stability, enhanced write ability, and suppressed leakage power consumption as compared to previously published six-FinFET memory circuits. With the new SRAM cell, the read data stability, read speed, write voltage margin, and write speed are enhanced by up to 2.7×, 57.6%, 25.5%, and 20.1% while the leakage power consumption is reduced by up to 69.8% without degrading the memory integration density as compared to the previously published six-FinFET SRAM cells in a 15nm FinFET technology.