Characterization of Single Bit and Multiple Cell Soft Error Events in Planar and FinFET SRAMs

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Abstract
We characterize soft errors of SRAM devices fabricated over a range of technology nodes and show that both single-bit upsets (SBUs) and multiple-cell upsets (MCUs) decrease with technology scaling. Implementation of FinFET transistors leads to a significant reduction in both SBUs and MCUs relative to planar transistors. We find the mechanisms responsible for SBU and MCU events are unaffected by the transition to the FinFET architecture. For errors due to alpha particles and thermal neutrons, the relative occurrence of single event upsets is determined primarily by the sensitive area of the drain of bit cell transistors. We show that high-energy neutron-induced MCU events are determined by charge sharing among adjacent cells and are sensitive to both transistor drain area and the details of the process technology (i.e., manufacturing sequence) used, via the dependence of charge mobility on the substrate doping level.

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