Realizing On/Off Ratios over 104 for Sub-2 nm Vertical Transistors
- 30 August 2023
- journal article
- research article
- Published by American Chemical Society (ACS) in Nano Letters
- Vol. 23 (17) , 8303-8309
Abstract
Vertical transistors hold promise for the development of ultrascaled transistors. However, their on/off ratios are limited by a strong source-drain tunneling current in the off state, particularly for vertical devices with a sub-5 nm channel length. Here, we report an approach for suppressing the off-state tunneling current by designing the barrier height via a van der Waals metal contact. Via lamination of the Pt electrode on a MoS2 vertical transistor, a high Schottky barrier is observed due to their large work function difference, thus suppressing direct tunneling currents. Meanwhile, this "low-energy" lamination process ensures an optimized metal/MoS2 interface with minimized interface states and defects. Together, the highest on/off ratios of 5 × 105 and 104 are realized in vertical transistors with 5 and 2 nm channel lengths, respectively. Our work not only pushes the on/off ratio limit of vertical transistors but also provides a general rule for reducing short-channel effects in ultrascaled devices.Keywords
Funding Information
- Natural Science Foundation of Hunan Province (2023JJ40171)
- National Key Research and Development Program of China (2021YFA1200503)
- China Postdoctoral Science Foundation (2023M731047)
- National Natural Science Foundation of China (51991340, 51991341, 52221001, U22A2074)
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