Likuan Ma

Two-dimensional (2D) vertical transistors, featuring atomically thin channels and an inherent vertical architecture, hold extensive promise for ultrascaled electronics. However, achieving reliable polarity control in such devices has remained a persistent challenge over the past decade. Here, we demonstrate a vertical MoTe2 transistor with highly controllable polarity. By implementing van der Waals (vdW) integration for both contacts, the carrier injection barrier can be effectively modulated via the work functions of the electrodes. Leveraging the favorable band alignment with graphene and the narrow bandgap of MoTe2, we achieve selective n-type and p-type operation using Ag and Pt top contacts, respectively. Furthermore, through graphene work-function engineering, we optimize the switching performance, realizing an on/off ratio exceeding 104 in a ∼5 nm p-type MoTe2 vertical transistor, surpassing all previously reported p-type 2D vertical transistors based on graphene/TMD/metal architectures. Finally, we integrate two vertical transistors of opposite polarities, fabricated from graphene/MoTe2 heterostructure with different top contacts, to demonstrate a complementary inverter on a single chip. Our work not only provides a viable strategy for polarity control in vertical heterostructures but also suggests a potential pathway toward complementary circuits based on 2D vertical transistors.

Inspired by avian vision, we present an organic ultraviolet-selective phototransistor. The lithium-ion solid-state electrolyte lithium lanthanum zirconium oxide (LLZO), which has high stability at room temperature, is applied as the dielectric layer of a transistor device. The device achieved an operating voltage below 4 V and a current on/off ratio reaching 2.04 × 109, with the subthreshold swing in the linear region as low as 61.39 mV dec–1. Because of the selective absorption of the active layer in the ultraviolet region, a pronounced photoresponse under ultraviolet illumination is observed. The mobile Li+ ions in the LLZO dielectric layer can attract electrons near the interface, dynamically modulating photogenerated carrier transport. Based on the organic ultraviolet-selective transistor array, the perceptual differences between human and avian vision under visible and ultraviolet light are simulated, offering a conceptual pathway for advancing artificial vision systems.

Epitaxy of perovskite single crystals (SCs) has gained development, rendering large-area monocrystalline films with decent quality and high uniformity, while its patterning technologies have fallen behind due to materials degradation and contamination when processing, limiting the achievement of perovskite SC arrays and pixelization on a large scale. Here, we report a patterning method that utilizes a rigid stamper with designed geometries to mechanically punch freestanding perovskite films into SC arrays, leading to the dry patterning of perovskite SCs with high uniformity and intrinsic properties. Furthermore, arrays of complex configurations could be integrated via van der Waals (vdW) lamination, building up full-color pixel and vertical heterostructure. Based on this, we fabricated 3 × 3 photodetector arrays, with all devices exhibiting a similar responsivity of 0.5-2.6 A/W, a detectivity of 0.3-4 × 10¹¹ Jones and a fast response time of sub-20 ms. This damage- and residue-free dry imprinting transfer approach not only establishes a simple and rapid method for patterning perovskite SC arrays on a large scale, which is important for high-performance photodetectors and other optoelectronics, but also demonstrates potential for the integration of optoelectronics based on delicate semiconductors including organic thin films, 2D magnetic crystals, as well as their vdW heterostructures that are not compatible with conventional patterning techniques following the lithography-etching routine.

Plasma treatment has been widely used to improve the performance of oxide transistors. However, the real active channel of the back-gated transistors is typically buried close to the dielectric interface and cannot be effectively modulated by plasmas. In this work, we report a bottom plasma treatment strategy that can directly modulate the oxide channel. Within this process, the as-deposited oxide channel could be physically peeled off from the sacrificial wafer using the van der Waals delamination process, exposing the bottom channel region for direct plasma treatment. After treatment, indium gallium zinc oxide (IGZO) transistors exhibit a large on-off ratio of 4 × 10⁸ and high carrier mobility over 25 cm² V^-1 s^-1, which is over 4 times higher compared to the control device with conventional top plasma treatment. Furthermore, detailed X-ray photoelectron spectroscopy measurements confirm that the improved performance originates from the passivation of oxygen vacancy and nitrogen doping within the active bottom channel region.

Two-dimensional (2D) semiconductors have attracted a considerable amount of interest as channel materials for future transistors. Patterning of 2D semiconductors is crucial for separating continuous monolayers into independent units. However, the state-of-the-art 2D patterning process is largely based on photolithography and high-energy plasma/RIE etching, leading to unavoidable residues and degraded device uniformity, which remains a critical challenge for the practical application of 2D electronics. Here, we report a polymer-free and dry-patterning technique for wafer-scale 2D semiconductors. Upon lamination of a three-dimensional Au stamp onto monolayer MoS₂ and then it being peeled away, the Au-contacted region will be effectively removed while the noncontacted regions are successfully left on its growth substrate. The fabricated MoS₂ transistors exhibit a 100% device yield, increased carrier mobility, and much reduced device-to-device variation, compared to those of conventional wet-patterned devices. Our work provides a simple and rapid dry-patterning technique for 2D wafers, which is important for the lab-to-fab transition.

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as highly promising candidates for next-generation electronics owing to their atomically thin structures and surfaces devoid of dangling bonds. However, establishing high-quality metal contacts with TMDs presents a critical challenge, primarily attributed to their ultrathin bodies and delicate lattices. These distinctive characteristics render them susceptible to physical damage and chemical reactions when conventional metallization approaches involving "high-energy" processes are implemented. To tackle this challenge, the concept of van der Waals (vdW) contacts has recently been proposed as a "low-energy" alternative. Within the vdW geometry, metal contacts can be physically laminated or gently deposited onto the 2D channel of TMDs, ensuring the formation of atomically clean and electronically sharp contact interfaces while preserving the inherent properties of the 2D TMDs. Consequently, a considerable number of vdW contact devices have been extensively investigated, revealing unprecedented transport physics or exceptional device performance that was previously unachievable. This review presents recent advancements in vdW contacts for TMD transistors, discussing the merits, limitations, and prospects associated with each device geometry. By doing so, our purpose is to offer a comprehensive understanding of the current research landscape and provide insights into future directions within this rapidly evolving field.

Van der Waals heterostructures (vdWHs) based on two-dimensional (2D) semiconductors have attracted considerable attention. However, the reported vdWHs are largely based on vertical device structure with large overlapping area, while the realization of lateral heterostructures contacted through 2D edges remains challenging and is majorly limited by the difficulties of manipulating the lateral distance of 2D materials at nanometer scale (during transfer process). Here, we demonstrate a simple interfacial sliding approach for realizing an edge-by-edge lateral contact. By stretching a vertical vdWH, two 2D flakes could gradually slide apart or toward each other. Therefore, by applying proper strain, the initial vertical vdWH could be converted into a lateral heterojunction with intimately contacted 2D edges. The lateral contact structure is supported by both microscope characterization and in situ electrical measurements, exhibiting carrier tunneling behavior. Finally, this approach can be extended to 3D thin films, as demonstrated by the lateral 2D/3D and 3D/3D Schottky junction.

Two-dimensional (2D) semiconductors have generated considerable attention for high-performance electronics and optoelectronics. However, to date, it is still challenging to mechanically exfoliate large-area and continuous monolayers while retaining their intrinsic properties. Here, we report a simple dry exfoliation approach to produce large-scale and continuous 2D monolayers by using a Ag film as the peeling tape. Importantly, the conducting Ag layer could be converted into AgO_x nanoparticles at low annealing temperature, directly decoupling the conducting Ag with the underlayer 2D monolayers without involving any solution or etching process. Electrical characterization of the monolayer MoS₂ transistor shows a decent carrier mobility of 42 cm² V^-1 s^-1 and on-state current of 142 μA/μm. Finally, a plasmonic enhancement photodetector could be simultaneously realized due to the direct formation of Ag nanoparticles arrays on MoS₂ monolayers, without complex approaches for nanoparticle synthesis and integration processes, demonstrating photoresponsivity and detectivity of 6.3 × 10⁵ A/W and 2.3 × 10¹³ Jones, respectively.

Vertical transistors hold promise for the development of ultrascaled transistors. However, their on/off ratios are limited by a strong source-drain tunneling current in the off state, particularly for vertical devices with a sub-5 nm channel length. Here, we report an approach for suppressing the off-state tunneling current by designing the barrier height via a van der Waals metal contact. Via lamination of the Pt electrode on a MoS₂ vertical transistor, a high Schottky barrier is observed due to their large work function difference, thus suppressing direct tunneling currents. Meanwhile, this "low-energy" lamination process ensures an optimized metal/MoS₂ interface with minimized interface states and defects. Together, the highest on/off ratios of 5 × 10⁵ and 10⁴ are realized in vertical transistors with 5 and 2 nm channel lengths, respectively. Our work not only pushes the on/off ratio limit of vertical transistors but also provides a general rule for reducing short-channel effects in ultrascaled devices.