Compact test sets for high defect coverage
Authors:
- S.M. ReddySRS.M. Reddy
- I. PomeranzIPI. Pomeranz
- S. KajiharaSKS. Kajihara
- 1 January 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 16 (8) , 923-930
Abstract
No abstract availableThis publication has 5 references indexed in Scilit:
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- SOCRATES: a highly efficient automatic test pattern generation systemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978