Quiescent current estimation for current testing
Authors:
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 543-548
Abstract
Logic voltage testing has some limitations dealing with defects that turn digital into analog values. For these parametric faults, current testing is being considered as a promising complementary technique. A methodology to characterize the quiescent circuit consumption in a new way that simplifies the electrical simulation of a complex VLSI circuit is proposed. Further it is exemplified on the C17 IS-CAS circuit, concluding that the proposed method has been successful in the example and can be easily programmed to estimate I/sub ddq/ for large circuits without the well known electrical simulation time penalty.<>Keywords
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