Energy efficient parallel computing on the PULP platform with support for OpenMP
- 1 December 2014
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-5
Abstract
Many-core architectures structured as fabrics of tightly-coupled clusters have shown promising results on embedded parallel applications, providing state-of-art performance with a reduced power budget. We propose PULP (Parallel processing Ultra-Low Power platform), an architecture built on clusters of tightly-coupled OpenRISC ISA cores, with advanced techniques for fast performance and energy scalability that exploit the capabilities of the STMicroelectronics UTBB FD-SOI 28nm technology. To exploit thread level parallelism of applications PULP supports a lightweight implementation of OpenMP 3.0 running on a bare metal runtime optimized for embedded architectures. The proposed platform demonstrates able to provide high performance for a wide range of workloads ranging from 1.2 MOPS to 3 GOPS with a peak energy efficiency of 210 GOPS/W. Thanks to the efficient exploitation of forward and reverse body biasing on fine grained regions of the cluster, the platform is able to improve by up to 1.3x the energy efficiency of parallel portions, and by up to 2.4x the energy efficiency of sequential portions of OpenMP applications.Keywords
This publication has 18 references indexed in Scilit:
- Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes2014
- Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters2014
- Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory2014
- A Fine-Grain Variation-Aware Dynamic ${\rm Vdd}$-Hopping AVFS Architecture on a 32 nm GALS MPSoCIEEE Journal of Solid-State Circuits, 2014
- Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOSIEEE Journal of Solid-State Circuits, 2013
- P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator2012
- Supporting OpenMP on a multi-cluster embedded MPSoCMicroprocessors and Microsystems, 2011
- A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters2011
- Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal ProcessingLecture Notes in Computer Science, 2011
- Diet SODA2010