Design considerations of a fast 0-Ω gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration
Authors:
- 1 September 2009
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 23293721,p. 2293-2300
Abstract
This paper presents detailed design considerations of an ultra fast gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration using 0-Omega gate resistance. The proposed gate-drive achieved turn-on and turn-off times in the range of 12 to 55 ns operating from a 600 V dc bus with an inductive load of 10 A, and junction temperatures varying from 25deg to 200degC. An in-depth experimental evaluation is presented as well fully characterizing the performance attained by the proposed gate-drive circuit.Keywords
This publication has 11 references indexed in Scilit:
- Design and Performance of a 200 kHz All-SiC JFET Current Source Converter2008
- Silicon carbide power semiconductors — new opportunities for high efficiency2008
- Comprehensive Design of a Three-Phase Three-Switch Buck-Type PWM RectifierIEEE Transactions on Power Electronics, 2007
- Ultra Compact Three-phase PWM Rectifier2007
- Three-Phase Ac Buck Rectifier using Normally-On SiC JFETs at 150 kHz Switching Frequency2007
- A SiC JFET driver for a 5 kW, 150 kHz three-phase PWM converter2005
- Fast gate drive for SiC-JFET using a conventional driver for MOSFETs and additional protections2005
- A gate drive circuit for silicon carbide JFET2004
- A novel SiC J-FET gate drive circuit for sparse matrix converter applications2004
- Development and demonstration of silicon carbide (SiC) motor drive inverter modules2004