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  3. Design considerations of a fast 0-Ω gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration
  4. Publication with shared reference
  5. 10.1109/ecce.2009.5316075
  1. Home
  2. Publications
  3. Design considerations of a fast 0-Ω gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration
  4. Publication with shared reference
  5. 10.1109/ecce.2009.5316075

Publications with shared reference:

Design considerations of a fast 0-Ω gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration

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