Floorplan-aware analog IC sizing and optimization based on topological constraints
- 1 January 2015
- journal article
- Published by Elsevier in Integration
- Vol. 48, 183-197
Abstract
No abstract availableFunding Information
- Instituto de Telecomunicações (PEst-OE/EEI/LA0008/2013)
- Fundação para a Ciência e a Tecnologia (EXCL/EEI-ELC/0261/2012, FCTSFRH/BD/86608/2012, FCT-DFRH-SFRH/BD/72698/2010)
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