A Two-Step ADC With Statistical Calibration
- 16 March 2020
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 67 (8) , 2588-2601
Abstract
This paper describes a prototype two-step ADC with adjustable resolution in 40 nm CMOS technology. It uses a front-end successive-approximation-register ADC and a back-end time-domain ADC. Digital statistical calibration overcomes errors from front-end mismatch as well as inter-stage and back-end nonlinearity by analyzing specific statistical properties. In the 12-bit mode at 20 MS/s, the maximum SNDR is 59 dB before calibration and 68 dB after calibration, using 6.2 fJ per conversion-step, excluding the power dissipation required by the calibration.Keywords
Funding Information
- Analog Devices
- Keysight Technologies
- Northrop Grumman
- NSF (1444086)
- Qualcomm
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