A Quantum-Well Charge-Trap Synaptic Transistor With Highly Linear Weight Tunability

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Abstract
In this work, a novel synaptic transistor has been proposed and analyzed through technology computer-aided design (TCAD) simulation. The proposed device has merits of full-Si processing compatibility, short-and long-term plasticity, high energy efficiency, and linear and symmetric conductance adjustability. The proposed device consists of a quantum-well structure and a charge-trap unit for realizing both short-and long-term memories, respectively. The quantum-well charge-trap synaptic transistor (QW CTS) employs two independent gates to separate inference and weight adjustment operation. An optimally designed and validated QW CTS has demonstrated a highly linear and symmetric weight tunability, with an ultra-low energy consumption of 1.5 fJ per synaptic event. The QW CTS can be a core element in the hardware-driven Si neuromorphic system.
Funding Information
  • Nano-Material Technology Development Program through the National Research Foundation (NRF) funded by the Ministry of Science and ICT (NRF-2016M3A7B4910348)
  • Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Korea Government (2020-0-01294-001)

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