Eunseon Yu

Achieving multi-level devices is crucial to efficiently emulate key bio-plausible functionalities such as synaptic plasticity and neuronal activity, and has become an important aspect of neuromorphic hardware development. In this review article, we focus on various ferromagnetic (FM) and ferroelectric (FE) devices capable of representing multiple states, and discuss the usage of such multi-level devices for implementing neuromorphic functionalities. We will elaborate that the analog-like resistive states in ferromagnetic or ferroelectric thin films are due to the non-coherent multi-domain switching dynamics, which is fundamentally different from most memristive materials involving electroforming processes or significant ion motion. Both device fundamentals related to the mechanism of introducing multilevel states and exemplary implementations of neural functionalities built on various device structures are highlighted. In light of the non-destructive nature and the relatively simple physical process of multi-domain switching, we envision that ferroic-based multi-state devices provide an alternative pathway toward energy efficient implementation of neuro-inspired computing hardware with potential advantages of high endurance and controllability.

In this work, a novel synaptic transistor has been proposed and analyzed through technology computer-aided design (TCAD) simulation. The proposed device has merits of full-Si processing compatibility, short-and long-term plasticity, high energy efficiency, and linear and symmetric conductance adjustability. The proposed device consists of a quantum-well structure and a charge-trap unit for realizing both short-and long-term memories, respectively. The quantum-well charge-trap synaptic transistor (QW CTS) employs two independent gates to separate inference and weight adjustment operation. An optimally designed and validated QW CTS has demonstrated a highly linear and symmetric weight tunability, with an ultra-low energy consumption of 1.5 fJ per synaptic event. The QW CTS can be a core element in the hardware-driven Si neuromorphic system.

In order to resolve the issue of tremendous energy consumption in conventional artificial intelligence, hardware-based neuromorphic system is being actively studied. Although various synaptic devices for the system have been proposed, they have shown limits in terms of endurance, reliability, energy efficiency, and Si processing compatibility. In this work, we design a synaptic transistor with short-term and long-term plasticity, high density, high reliability and energy efficiency, and Si processing compatibility. The synaptic characteristics of the device are closely examined and validated through technology computer-aided design (TCAD) device simulation. Consequently, full synaptic functions with high energy efficiency have been realized.

A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor (MOSFET) with heavily-doped n+ source and drain junctions, nearly intrinsic n- channel, 500-nm gate length (LG), and 50-nm poly-Si body thickness (Tbody). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by grain boundaries (GBs) capable of charge trapping not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of 3.2 μA/μm and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems.

In this paper, a p-type inverted-T FinFET (IT FinFET) has been optimally structured. Focus is made on analyzing the inferior characteristics reported from the previously fabricated IT FinFETs, and obtaining better performances through a novel structure. IT FinFET has a higher layout efficiency and can thus provide larger drain current (I _D ) under the same dimension as that of a silicon-on-insulator (SOI) FinFET by securing the extended channels of ultrathin body (UTB) on the field region. We closely observe the leverages of fin width (W _fin ), UTB height (H _UTB ), and gate length (L _g ) on the operation characteristics using a 3-D technology computer-aided design simulation with quantum-mechanical models. W _fin below 10 nm is evaluated to be suitable for strong gate controllability.We first examine a critical H _UTB , beyond which a higher drive current is not obtained even with a greater channel width than that of FinFET. When H _UTB = 3 and 10 nm, IT FinFET yields 13.3% and 142% of saturation current improvement compared with SOI FinFET under the same footprint. At extremely scaled L _g , although the immunity against short-channel effects is slightly weaker than that of SOI FinFET, optimally designed IT FinFET can produce a higher current and demonstrates shorter intrinsic delay times.