CMOS differential pass-transistor logic design
Authors:
- J.H. PasternakJPJ.H. Pasternak
- A.S. ShubatASA.S. Shubat
- C.A.T. SalamaCSC.A.T. Salama
- 1 April 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (2) , 216-222
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- Computer-Aided Minimization Procedure for Boolean FunctionsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Differential pass transistor logic in CMOS technologyElectronics Letters, 1986
- Digital CMOS Circuit Design1986
- Formal design procedures for pass transistor switching circuitsIEEE Journal of Solid-State Circuits, 1985
- Cascode voltage switch logic: A differential CMOS logic family1984