A 200 MHz 1.22 fJ/bit/search single-ended content addressable memory cell design in 45-nm CMOS technology

This publication has 40 references indexed in Scilit:

• A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process
  2023
• Experimental Demonstration of a Ferroelectric HfO₂-Based Content Addressable Memory Cell
  IEEE Electron Device Letters, 2019
• A review of emerging industry 4.0 technologies in remanufacturing
  Journal of Cleaner Production, 2019
• A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier
  IEEE Journal of Solid-State Circuits, 2019
• Design and analysis of 2T-2M Ternary content addressable memories
  2017
• Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories
  Proceedings of the IEEE, 2015
• A match-line dynamic energy reduction technique for high-speed ternary CAM using dual feedback sense amplifier
  Microelectronics Journal, 2014
• A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS
  IEEE Journal of Solid-State Circuits, 2013
• A 65 nm 0.165 fJ/Bit/Search 256$\,\times\,$144 TCAM Macro Design for IPv6 Lookup Tables
  IEEE Journal of Solid-State Circuits, 2010
• A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme
  IEEE Journal of Solid-State Circuits, 2003