Ralph Gerard B. Sangalang

This paper presents a high-performance embedded micro-sensing and processing integrated non-intrusive load monitoring system for real-time appliance health assessment and remaining useful life (RUL) prediction, with the core innovation focused on the design and implementation of an STM32H7-based embedded micro-system that realizes seamless integration of high-frequency signal acquisition, edge-side real-time preprocessing, and intelligent multi-task analysis on a single chip. Utilizing an STM32H7 microcontroller, it captures high-frequency voltage and current signals to detect appliance degradation features. Time-frequency preprocessing with FFT and STFT improves signal representation, enabling better feature extraction. The proposed DRN-Transformer model integrates deep residual networks and Transformer attention mechanisms to extract both local and long-range temporal features. Tested on four common household appliances (refrigerator, washing machine, air conditioner, microwave oven), the system achieved over 92 % accuracy in health classification (up to 97.8 % for washing machines) and a low error in RUL estimation with an average RMSE of 3.2 months and an average MAPE of 8.5 %, outperforming traditional machine learning baselines (SVM/RF) by more than 40 % in health classification accuracy and surpassing mainstream deep learning models (LSTM/Transformer/LSTM-VMD) by 15-20 % in RUL prediction precision. Furthermore, the proposed embedded micro-sensing platform explicitly considers hardware-level constraints such as on-chip memory capacity, computational complexity, and real-time inference latency. By optimizing model architecture and adopting lightweight deployment strategies, the system achieves efficient edge-side intelligence while maintaining compatibility with resource-constrained microcontroller platforms. The system outperformed traditional baseline models and showed good generalization across different brands. With low latency and power consumption, it is well-suited for smart home applications.

Physical unclonable functions (PUFs) are increasingly recognized as a key technology for enhancing hardware and the Internet of Things (IoT) security. The IoT devices are often plagued by weak security measures, making them susceptible to various external threats. To address these vulnerabilities, robust and reliable security solutions are critical. This study introduces a highly reliable and low-power PUF application-specific integrated circuit (ASIC) design specifically designed for the IoT security applications. Initially, the proposed design is deployed on a Xilinx ZYNQ 7000 field-programmable gate array (FPGA) board operating at 100 MHz and later designed and fabricated using the Cadence Innovus in the 180-nm CMOS process on silicon. This work presents and evaluates a novel xnor–xor ring oscillator (RO) PUF with a configurable frequency. The design’s performance is analyzed using statistical metrics, including reliability, uniqueness, and uniformity. The xnor–xor RO PUF ASIC demonstrates max reliability of 91.92%, a uniqueness of 49.62%, and a uniformity of 50.19% on silicon.

DNN (deep neural network) and CNN (convolution neural network) have been widely used in real-time artificial intelligent (AI) applications, particularly image or video recognitions, because they have been proved physically in many occasions. However, most prior AI hardware works are either suffered from high on-silicon area cost or low usage thereof. This investigation presents a power efficient and high performance implementation of a digital logic accelerator (DLA) for the underwater real-time underwater object recognition. The proposed DLA is also featured with 2-dimensional PE (processing element) array to increase the processing throughput by the enhancement of parallelism. The DLA design was realized and fabricated using TSMC 40-nm CMOS process. Not only the post-layout simulation results are shown, the on-silicon measurement outcome as well as the system validation in water are also demonstrated to prove the function correctness and the performance. The area efficiency (GOPS/mm²) is 4.562, and the power efficiency (TOPS/W) is 0.5668 on silicon, which both are the best to date.