In-Memory Realization of Balanced Ternary Logic Gates and Decoders Using the Resistance States of Tri-Valued Memristors

Memristors have attracted considerable attention as promising candidates for in-memory computing due to their non-volatile properties. Conventional CMOS devices support only two states (on and off) and therefore cannot directly realize the three distinct states required by ternary logic. In contrast, tri-valued memristors (TMRs) inherently possess three stable resistance states, which can be naturally mapped to the three logic variables of ternary logic, such as \(\{-1, 0, 1\}\) in balanced ternary logic. Compared with binary logic, ternary logic provides higher information density and computational efficiency under the same hardware scale, thereby reducing circuit complexity and power consumption. In this paper, balanced ternary logic gate circuits including the ternary OR gate, three types of ternary inverters and the ternary univariate logic function \(F_2\) circuit are designed using TMRs. By analyzing the commonalities of these circuits, a general circuit configuration is derived, enabling consistent implementation within memristor arrays. Furthermore, a balanced ternary 1-3 decoder is developed based on the proposed gates. All of these circuits are implemented in a 1T1M TMR crossbar array, and their functionality is verified through LTspice simulations.