Xiaoyuan Wang

As a nano-scale, non-volatile device compatible with CMOS technologies, the memristor is well suited for in-memory computing and provides a new venue for accelerating neural network computing. However, memristor-based neural networks are typically based on continuous-type memristors or binary memristors. Continuous-type memristors require precise voltage amplitude and duty cycle for setting resistance, which increases the difficulty of practical applications, whereas binary memristors provide limited weight accuracy due to their restricted two memrisitance states. In contrast, tri-valued memristors feature three discrete resistance values, enabling them to represent a broader range of weight states and allowing a more straightforward resistance setting mechanism. This leads to a better balance between the hardware feasibility and the weight representation capacity of the artificial neural network. This paper proposes a ternary neural network design scheme based on tri-valued memristors. The design scheme consists of a fully hardware-based forward computing circuit using a tri-valued memristor crossbar array, a tri-valued memristance-based weight setting method, a weight updating algorithm for the ternary quantized neural network, an activation function circuit, and a winner-take-all (WTA) circuit. This design features the natural synaptic characteristics of memristors and the computational advantages of the quantized neural network, facilitating a hardware platform and a feasible implementation scheme for lightweight all-hardware neural circuit design. The scheme verified with LTSpice circuit simulations enables correct recognition of test characters ‘z’, ‘v’, and ‘n’. Furthermore, it is extended to the LeNet-5 network on the MemTorch platform, achieving a recognition accuracy of 98.47% in the MNIST benchmark test.

Balanced ternary digital logic circuits are designed based on memristors and applied to realize adder circuits, which can alleviate the Von Neumann architecture bottleneck and help extend Moore's Law. Four design methods are presented: decoder‐based method, multiplexer‐based method, method of combining multiplexers with single variable logic circuits, and method based on digital logic gates. The full‐adder circuits implemented by the above four distinct design methods are systematically compared and analyzed. This analysis highlights the strengths and limitations of each approach, thus providing a guideline for future development and optimization of balanced ternary combinational logic circuits aimed at achieving enhanced performance, power efficiency, and compactness.

This paper proposes a novel neuronal circuit and a Pavlov associative memory network based on memristors, which possesses various characteristics such as adjustable conductance and can effectively simulate the synaptic connection strength between neurons in a neural network. Furthermore, this paper designs a corresponding digital logic circuit for the Pavlovian associative memory task to reproduce the associative memory process observed in Pavlov’s experiments. Experimental results show that the proposed circuit can accurately implement associative memory and weight modulation, and can simulate the Pavlovian associative memory process. Combining memristor-based synaptic circuits and memristor-Complementary Metal Oxide Semiconductor digital logic gates, an associative memory circuit with modularity and simple structure is realized and verified using LTSpice. The proposed circuit realizes the basic learning and forgetting functions of Pavlovian associative circuits, which provides a novel circuit implementation form for further research based on Pavlovian association.

Balanced ternary digital logic circuits based on memristors and MOSFET devices are introduced. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are designed and verified by simulation. Next, logic circuits such as ternary encoders, decoders and multiplexers are designed using these three basic gates. For further validation, a ternary 3-1 encoder was hardware-implemented successfully using in-house fabricated memristors and MOS transistors. Two different design approaches, namely the decoder-based method and the multiplexer-based method are introduced and applied to realize combinational logic circuits such as balanced ternary half-adder, multiplier, and numerical comparator. We simulate the circuits using 50nm CMOS technology parameters and BSIM models and present comparisons and analyses of the two design methods in view of the power consumption and component device counts, which can guide subsequent research and development of integrated multi-valued logic circuits. The decoder-based method has advantages both in terms of component numbers and power consumption, but the multiplexer-based method has the advantages of being based on a simple operating principle and ease of implementation.