A Segmented Gate Driver for E-mode GaN HEMTs with Simple Driving Strength Pattern Control
- 1 September 2020
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 102-105
Abstract
Gate overshoot voltage prevention when driving E-mode GaN-based HEMTs is essential for system reliability and EMI suppression. Active gate drivers have been demonstrated to suppress gate voltage overshoot while maintaining fast turn-on. However, they normally require complex driving patterns that are determined using trial and error approaches. In this paper, an active gate driver with an integrated pattern generator is proposed to simplify the control of the dynamic gate driving strength pattern. For best trade-off between overshoot and transition speed, the gate resistance (or gate driving strength) must remain low but with a large resistance switched in briefly during the turn-on transition period. Switch timing of the driving pattern varies with load conditions and the types of transistor. To simplify the programming of the driving pattern, the gate driving strength can be controlled by changing only one external bias resistor in the proposed design. This in turn sets the bias current of a delay chain to adjust the timing of the gate driving strength pattern. The proposed design aims to create a systematic approach to simplify the selection of the gate driving strength pattern.Keywords
This publication has 6 references indexed in Scilit:
- Stretching in Time of GaN Active Gate Driving Profiles to Adapt to Changing Load Current2018
- Application reliability validation of GaN power devices2016
- Review of Commercial GaN Power Devices and GaN-Based Converter Design ChallengesIEEE Journal of Emerging and Selected Topics in Power Electronics, 2016
- 16.7 A 20V 8.4W 20MHz four-phase GaN DC-DC converter with fully on-chip dual-SR bootstrapped GaN FET driver achieving 4ns constant propagation delay and 1ns switching rise time2015
- A segmented output stage H-bridge IC with tunable gate driver2014
- A monotonic digitally controlled delay elementIEEE Journal of Solid-State Circuits, 2005