A segmented output stage H-bridge IC with tunable gate driver

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Abstract
In this paper, an integrated EDMOS H-bridge that incorporates both segmented output transistors and segmented gate drivers is presented. This fully segmented design approach allows the output resistance of the H-bridge and the output resistance of the gate drivers to be dynamically adjusted. Dynamic adjustment of these parameters allows for the continuous optimization of the power conversion efficiency of the H-bridge over a wide range of output currents. The IC chip is fabricated using TSMC's 0.18 μm BCD Gen-2 process technology. The H-bridge is operated with a 10 V input, 2 V output and a load current between 0.02 A and 4 A. The presented design achieves power conversion efficiency improvements of 32% and 8% at light load current and heavy load current, respectively, when compared to traditional fixed power transistor designs. Furthermore, the dynamically adjustable output resistance of the gate drivers allows for suppression of switching node ringing and conducted EMI (CEMI) by 5.5 dB with no a significant reduction in efficiency.