Innovative Circuit Board Level Routing Designs for BGA Packages
Authors:
- T.J. DishonghTDT.J. Dishongh
- A.N. CartwrightACA.N. Cartwright
- 15 November 2004
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Advanced Packaging
- Vol. 27 (4) , 630-639
Abstract
Advances in the performance of electronic devices have resulted in high input/output counts both at the chip and the package level, which has led to the development of new packaging technologies that can accommodate these high counts. This paper presents and analyzes a novel method for the placement of ball grid array (BGA) bonding pads and routing wires on printed circuit boards to maximize signal density, which ultimately reduces the number of circuit board layers needed for routing. This method has been termed as the "balls shifted as needed" method and all the ball placement/trace routing designs shown in this paper are based on this method. We also present a performance metric defined as the number of balls routed out divided by the area of package footprint on the circuit board, and we compare various placement/routing schemes using this method.Keywords
This publication has 14 references indexed in Scilit:
- Early footprint comparison for area I/O packages and first level interconnect2003
- A method of designing a group of bumps for C4 packages to maximize the number of bumps and minimize the number of package layers2002
- Fast pad redistribution from periphery-IO to area-IO2002
- Understanding models of substrate behaviour for the routing of high I/O packages2002
- Pin assignment and routing on a single-layer pin grid array2002
- Escape routing design to reduce the number of layers in area array packagingIEEE Transactions on Advanced Packaging, 2000
- Optimal printed wiring board design for high I/O density chip size packagesCircuit World, 1999
- Hexagonal Models for Channel RoutingAlgorithmica, 1997
- Limitation of the signal pin density on wiring boardsIEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, 1996
- A provably good multilayer topological planar routing algorithm in IC layout designsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993