Three-dimensional cache design exploration using 3DCacti
Authors:
- Yuh-Fang TsaiYTYuh-Fang Tsai
- Yuan XieYXYuan Xie
- N. VijaykrishnanNVN. Vijaykrishnan
- M.J. IrwinMIM.J. Irwin
- 15 August 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 519-524
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- 3D processing technology and its impact on iA32 microprocessors2004
- SRAM design on 65nm CMOS technology with integrated leakage reduction scheme2004
- 2.5D system integration: a design driven system implementation schema2004
- Timing, energy, and thermal performance of three-dimensional integrated circuits2004
- Technology, performance, and computer-aided design of three-dimensional integrated circuits2004
- Contact Resistance Measurement of Bonded Copper Interconnects for Three-Dimensional Integration TechnologyIEEE Electron Device Letters, 2004
- Analytical models for leakage power estimation of memory array structures2004
- The revolutionary and truly 3-dimensional 25F/sup 2/ SRAM technology with the smallest S/sup 3/ ( stacked single-crystal Si) cell, 0.16um/sup 2/, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAM2004
- 3D direct vertical interconnect microprocessors test vehicle2003
- Networks on chips: a new SoC paradigmComputer, 2002