A Novel Multiplexer-Based Low-Power Full Adder
Authors:
- A. Al-SheraidahAAA. Al-Sheraidah
- Yuke WangYWYuke Wang
- E. ShaESE. Sha
- Jin-Gyun ChungJCJin-Gyun Chung
- 19 July 2004
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
- Vol. 51 (7) , 345-348
Abstract
The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster.Keywords
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