Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs
Authors:
- K. PaulssonKPK. Paulsson
- M. HubnerMHM. Hubner
- M. JungMJM. Jung
- J. BeckerJBJ. Becker
- 10 March 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs2005
- Online BIST and BIST-based diagnosis of FPGA logic blocksIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004
- Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration2004
- An FPGA run-time system for dynamical on-demand reconfiguration2004