BIST-based delay path testing in FPGA architectures
Authors:
- I.G. HarrisIHI.G. Harris
- P.R. MenonPMP.R. Menon
- R. TessierRTR. Tessier
- 13 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 932-938
Abstract
No abstract availableKeywords
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