On test data volume reduction for multiple scan chain designs
Authors:
- K. MiyaseKMK. Miyase
- S. KajiharaSKS. Kajihara
- I. PomeranzIPI. Pomeranz
- 25 June 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 103-108
Abstract
We consider issues related to the reduction of scan test data in designs with multiple scan chains. We propose a metric that can be used to evaluate the effectiveness of procedures for reducing the scan data volume. The metric compares the achieved compression to the compression which is intrinsic to the use of multiple scan chains. We also propose a procedure for modifying a given test set so as to achieve reductions in test data volume assuming a combinational decompressor circuit.Keywords
This publication has 9 references indexed in Scilit:
- Scan vector compression/decompression using statistical coding2003
- Reducing test application time for full scan embedded cores2003
- On identifying don't care inputs of test patterns for combinational circuits2002
- Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression2002
- Virtual scan chains: a means for reducing scan length in cores2002
- Test volume and application time reduction through scan chain concealment2001
- Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registersIEEE Transactions on Computers, 1995
- Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
- COMPACTEST: a method to generate compact test sets for combinational circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993