Hysteresis-Free Carbon Nanotube Field-Effect Transistors
Authors:
- Rebecca S. ParkRPRebecca S. Park
- Gage HillsGHGage Hills
- Joon SohnJSJoon Sohn
- Subhasish MitraSMSubhasish Mitra
- H.-S. Philip WongHWH.-S. Philip Wong
- 4 May 2017
- journal article
- research article
- Published by American Chemical Society (ACS) in ACS Nano
- Vol. 11 (5) , 4785-4791
Abstract
While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.Keywords
Funding Information
- Defense Advanced Research Projects Agency
- Kwanjeong Educational Foundation
- Intel Corporation
- Microelectronics Advanced Research Corporation
- Semiconductor Research Corporation
- National Science Foundation (CCF-0702343, CCF-0726791, CNS-1059020, ECCS-0954423)
- Systems on Nanoscale Information Fabrics
- member companies of Stanford SystemX Alliance
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