FPGA-Based AI-Driven Hardware-in-the-Loop Platform for Low-Latency Real-Time ABS ECU Testing

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Abstract
This paper presents an FPGA-based hardware-in-the-loop (HIL) platform for real-time simulation testing of anti-lock braking system (ABS) electronic control units (ECUs). The proposed system integrates a Temporal Convolutional Network (TCN) model implemented on FPGA hardware to provide real-time predictions of wheel speed sensors under complex braking scenarios. The FPGA acceleration achieves low-latency processing with a total end-to-end latency of 10.61 µs per prediction cycle, corresponding to approximately 94.3 Ksamples/s, which is suitable for closed-loop automotive testing. Experimental results show that the TCN model provides accurate prediction based on mean squared errors below 0.001043 for key parameters such as wheel speed sensors and lateral acceleration. The modular architecture of the simulator allows extensibility to other automotive ECUs and provides a scalable solution for real-time system validation in safety-critical applications.
Funding Information
  • Natural Sciences and Engineering Research Council of Canada

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