Paul Fortier

Cybersecurity has become one of the most critical challenges in the intelligent and connected vehicle ecosystem of today. As modern vehicles become increasingly connected and intelligent, the frequency and sophistication of cyberattacks targeting automotive systems continue to grow at an alarming rate. Ensuring robust detection and prevention mechanisms has therefore become essential to safeguard driver safety and vehicle integrity. Rapid and accurate identification of cyberthreats is critical, as such attacks can disrupt vital Electronic Control Units (ECUs) and compromise functions such as braking, steering, or communication networks. This review provides a comprehensive analysis of the major categories of cyberattacks targeting modern vehicles, including physical, remote, in-network, firmware- and software-based, cloud- and connectivity-related, and sensor-level perception attacks. Contemporary vehicle architectures, connected-vehicle technologies, software-update mechanisms, and current automotive cybersecurity standards and regulations are also considered. Although traditional cybersecurity testing approaches offer valuable insight into software vulnerabilities, they fail to capture the full cyber–physical interactions that govern vehicle behavior under malicious conditions. In this review, we highlight the essential role of Hardware-in-the-Loop (HIL) and Vehicle-in-the-Loop (VIL) platforms as realistic and safe environments for evaluating the impact of cyberattacks on automotive control systems and for generating synchronized cyber–physical data under controlled attack scenarios. We further examine how artificial intelligence (AI) techniques contribute to detecting, mitigating, and countering these cyberthreats, including supervised and unsupervised intrusion detection, deep-learning-based temporal modeling, cyber–physical anomaly detection, and the emerging challenge of adversarial attacks against AI-based detectors. By synthesizing insights from automotive cybersecurity, HIL-/VIL-based validation, automotive cybersecurity datasets, and AI-driven intrusion detection, this paper establishes a foundation for developing and evaluating more resilient and secure connected and software-defined vehicle architectures.

This paper presents an FPGA-based hardware-in-the-loop (HIL) platform for real-time simulation testing of anti-lock braking system (ABS) electronic control units (ECUs). The proposed system integrates a Temporal Convolutional Network (TCN) model implemented on FPGA hardware to provide real-time predictions of wheel speed sensors under complex braking scenarios. The FPGA acceleration achieves low-latency processing with a total end-to-end latency of 10.61 µs per prediction cycle, corresponding to approximately 94.3 Ksamples/s, which is suitable for closed-loop automotive testing. Experimental results show that the TCN model provides accurate prediction based on mean squared errors below 0.001043 for key parameters such as wheel speed sensors and lateral acceleration. The modular architecture of the simulator allows extensibility to other automotive ECUs and provides a scalable solution for real-time system validation in safety-critical applications.

The rapid evolution of modern vehicles into intelligent and interconnected systems presents new complexities in both functional safety and cybersecurity. In this context, ensuring the reliability and integrity of critical sensor data, such as wheel speed inputs for anti-lock brake systems (ABS), is essential. Effective detection of wheel speed sensor faults not only improves functional safety, but also plays a vital role in keeping system resilience against potential cyber–physical threats. Although data-driven approaches have gained popularity for system development due to their ability to extract meaningful patterns from historical data, a major limitation is the lack of diverse and representative faulty datasets. This study proposes a novel dual learning model, based on Temporal Convolutional Networks (TCN), designed to accurately distinguish between normal and faulty wheel speed sensor behavior within a hardware-in-the-loop (HIL) simulation platform implemented on an FPGA. To address dataset limitations, a TruckSim–MATLAB/Simulink co-simulation environment is used to generate realistic datasets under normal operation and eight representative fault scenarios, yielding up to 5000 labeled sequences (balanced between normal and faulty behaviors) at a sampling rate of 60 Hz. Two TCN models are trained independently to learn normal and faulty dynamics, and fault decisions are made by comparing the reconstruction errors (MSE and MAE) of both models, thus avoiding manually tuned thresholds. On a test set of 1000 sequences (500 normal and 500 faulty) from the 5000 sample configuration, the proposed dual TCN framework achieves a detection accuracy of 97.8%, a precision of 96.5%, a recall of 98.2%, and an F1-score of 97.3%, outperforming a single TCN baseline, which achieves 91.4% accuracy and an 88.9% F1-score. The complete dual TCN architecture is implemented on a Xilinx ZCU102 FPGA evaluation kit (AMD, Santa Clara, CA, USA), while supporting real-time inference in the HIL loop. These results demonstrate that the proposed approach provides accurate, low-latency fault detection suitable for safety-critical ABS applications and contributes to improving both functional safety and cyber-resilience of braking systems.

The increasing demand for cost-effective, high-speed Internet of Things (IoT) applications in the coming sixth-generation (6G) networks has driven research toward maximizing spectral efficiency and simplifying hardware designs. In this context, we investigate the sum rate maximization problem for a mode-switching discrete-phase shifters simultaneously transmitting and reflecting reconfigurable intelligent surface (STAR-RIS)-aided multi-antenna access point network, emphasizing hardware efficiency and reduced cost. A mixed-integer nonlinear optimization framework is formulated for joint optimization of the active beamforming matrix, user power allocation, and STAR-RIS phase shift vectors, including binary transmission/reflection amplitudes and discrete phase shifters. To solve the formulated problem, we employ a block coordinate descent method, dividing it into three subproblems tackled using difference-of-concave programming and combinatorial optimization techniques. Numerical results validate the effectiveness of the proposed joint optimization approach, consistently achieving superior sum rate performance compared to partial optimization methods, thereby underscoring its potential for efficient and scalable 6G IoT systems.

The increasing demand for cost-effective, high-speed Internet of Things (IoT) applications in the coming sixth-generation (6G) networks has driven research toward maximizing spectral efficiency and simplifying hardware designs. In this context, we investigate the sum rate maximization problem for a mode-switching discrete-phase shifters simultaneously transmitting and reflecting reconfigurable intelligent surface (STAR-RIS)-aided multi-antenna access point network, emphasizing hardware efficiency and reduced cost. A mixed-integer nonlinear optimization framework is formulated for joint optimization of the active beamforming matrix, user power allocation, and STAR-RIS phase shift vectors, including binary transmission/reflection amplitudes and discrete phase shifters. To solve the formulated problem, we employ a block coordinate descent method, dividing it into three subproblems tackled using difference-of-concave programming and combinatorial optimization techniques. Numerical results validate the effectiveness of the proposed joint optimization approach, consistently achieving superior sum rate performance compared to partial optimization methods, thereby underscoring its potential for efficient and scalable 6G IoT systems.

With the massive deployment of Internet of Things (IoT) devices in sixth-generation networks, several critical challenges have emerged, such as large communication overhead, coverage limitations, and limited battery lifespan due to high energy consumption. Federated learning (FL), wireless power transfer (WPT), multi-antenna access point (AP), and reconfigurable intelligent surfaces (RIS) can mitigate these challenges by reducing the need for large data transmissions, enabling sustainable energy harvesting, and optimizing the propagation environment. Compared to conventional RIS, simultaneously transmitting and reflecting (STAR)-RIS not only extends coverage from half-space to full-space but also improves energy saving through appropriate mode selection. Motivated by the need for sustainable, low-latency, and energy-efficient communication in large-scale IoT networks, this paper investigates the efficient STAR-RIS mode in the uplink and downlink phases of a WPT-FL multi-antenna AP network with non-orthogonal multiple access to minimize energy consumption, a joint optimization that remains largely unexplored in existing works on RIS or STAR-RIS. We formulate a non-convex energy minimization problem for different STAR-RIS modes, i.e., energy splitting (ES) and time switching (TS), in both uplink and downlink transmission phases, where STAR-RIS phase shift vectors, beamforming matrices, time and power for harvesting, uplink transmission, and downlink transmission, local processing time, and computation frequency for each user are jointly optimized. To tackle the non-convexity, the problem is decoupled into two subproblems: the first subproblem optimizes STAR-RIS phase shift vectors and beamforming matrices across all WPT-FL phases using block coordinate descent over either semi-definite programming or Rayleigh quotient problems, while the second one allocates time, power, and computation frequency via the one-dimensional search algorithms or the bisection algorithm. Simulation results demonstrate that TS STAR-RIS in both uplink and downlink transmissions achieves the lowest energy consumption, outperforming ES and conventional RIS schemes due to its flexible phase shift adaptation and lower interference levels.

Simultaneous transmitting and reflecting reconfigurable intelligent surfaces (STAR-RIS) introduces revolutionary capabilities by reaching full space coverage for wireless signals, significantly enhancing the efficiency and reliability of Internet of Things (IoT) networks compared to traditional RIS. In this paper, we propose a novel framework that leverages STAR-RIS into wirelessly powered federated learning (FL) networks with a multi-antenna access point, aiming to minimize system latency. A multi-variable non-convex optimization problem is formulated to optimize phase shift vectors of STAR-RIS, beamforming matrices, time, power, and computation frequency for each user in all phases of FL. Block coordinate descent (BCD) over the combination of a one-dimensional search algorithm and interior point method is employed to optimize time, power, computation frequency, phase shift vectors of STAR-RIS, and active beamforming matrix in the uplink transmission phase, while semi-definite relaxation via BCD addresses phase shift vectors of STAR-RIS and beamforming matrices optimization in harvesting and downlink transmission phases. On this basis, the optimized downlink transmission time and power are derived. The convergence of the proposed algorithm and the superiority of its performance compared to benchmark schemes are validated through comprehensive simulations. Our findings indicate the potential of FL, multi-antenna aggregation server, and STAR-RIS in ushering in a new era of intelligent and efficient IoT networks.

Due to the limited battery capacity and computational power of Internet-of-Things (IoT) devices, emerging IoT applications depend on mobile edge computing (MEC) networks for computational offloading and wireless power transfer (WPT) to sustain energy levels, with transfer performance influenced by the propagation environment and transmission strategies. Compared to the traditional reflecting-only reconfigurable intelligent surface (RIS), simultaneously transmitting and reflecting (STAR)-RIS extends coverage from half-space to full-space, significantly enhancing transferring efficiency. This paper compares the performance of three different uplink transmission schemes on a STAR-RIS WPT MEC network. On this basis, for each scenario, a non-convex optimization problem is formulated to maximize the total computational bits for the system, where energy transfer, local processing, uplink transmission allocated resources, and phase shift vectors of STAR-RIS are jointly optimized. To address the non-convexity, each scenario is decoupled into two main subproblems: phase shift vectors of STAR-RIS optimization and joint power, time, and computing frequency optimization. While a closed-form expression is derived to optimize the phase shift vector of STAR-RIS in time division multiple access (TDMA), semi-definite relaxation is employed to optimize the phase shift vectors under Hybrid TDMA- non-orthogonal multiple access (NOMA) and NOMA. Furthermore, block coordinate descent is employed to address the remaining resources. Simulation results indicate the superiority of the proposed scheme for all scenarios in terms of total computational bits compared to benchmark schemes. Moreover, among the three uplink transmission schemes, TDMA performs the best in total computational bits and user fairness owing to its ability to flexibly adapt STAR-RIS phase shift vectors.

System-on-chip (SoC) field programmable gate array (FPGA) devices are becoming increasingly prominent in a vast range of applications. The fusion of the FPGA’s unmatched parallel computing capacity and flexibility with a full-bore processing system makes these devices extremely powerful. With recent technological progress, SoC FPGA devices are implemented in increasingly complex systems where security and safety are often issues of concern. To cater to these concerns, these devices are commonly fit with encryption and authentication capabilities to ensure the confidentiality and authenticity of externally stored bitstreams, firmware, and bootloaders. However, while much effort is placed into securing these partitions when stored in external memory, little attention seems to be paid to the security of this data once it is decrypted for execution. This article investigates how vulnerable systems are to attacks that target decrypted data during execution. We demonstrate that data stored in external synchronous dynamic random access memory (SDRAM) can provide access to trusted and secured interfaces of SoC FPGA devices even with diligently applied security features.