Conventional gate-stack scaling reduces dielectric thickness and increases permittivity while largely treating the position and electronic character of the gate-side screening boundary as fixed. Here we show that this boundary can be engineered by converting the surface of the topological insulator Bi 2 Se 3 into insulating high-κ BiF 3 . Position-resolved calculations reveal a gap-opened immediate amorphous-BiF 3 /crystalline-Bi 2 Se 3 interface and a reconstructed gap-closed Bi 2 Se 3 -derived state in the adjacent subinterface layer, accompanied by a localized interfacial dipole. Capacitor measurements independently resolve a finite series response consistent with electronic compressibility at this boundary; this response lowers the nominal stack capacitance. Despite this capacitance penalty, MoS 2 transistors with closely matched BiF 3 thicknesses and a common BiF 3 /MoS 2 channel-side material interface exhibit near-thermionic-limit switching, negligible hysteresis and substantially weaker subthreshold drain-bias dependence than BiF 3 -only controls. These results identify the position and electronic character of the gate-side screening boundary as additional design variables for transistor electrostatics beyond nominal dielectric capacitance.