Information Flow Verification

This publication has 24 references indexed in Scilit:

• Toward Hardware Security Property Generation at Scale
  IEEE Security & Privacy, 2022
• Aker: A Design and Verification Framework for Safe and Secure SoC Access Control
  2021
• Spectre Attacks: Exploiting Speculative Execution
  2019
• Clepsydra: Modeling timing flows in hardware designs
  2017
• Towards Property Driven Hardware Security
  2016
• Leveraging Gate-Level Properties to Identify Hardware Timing Channels
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014
• SAT-Based Model Checking without Unrolling
  2011
• Language-based information-flow security
  IEEE Journal on Selected Areas in Communications, 2003
• Bounded Model Checking
  2003
• CSP and determinism in security modelling
  2002