Cynthia Sturton

Multi-Processor System-on-Chips (MPSoCs) are highly vulnerable to thermal attacks that manipulate dynamic thermal management systems (DTM). Specifically, this work focuses on thermal attacks launched by hardware Trojans that manipulate temperature sensor readings to either delay or falsely trigger thermal responses, undermining DTM systems. To counter this, we propose an adaptive real-time monitoring mechanism that detects abnormal thermal patterns in chip tiles. Our design space exploration identified key thermal features for an efficient anomaly detection module to be implemented at routers in network-enabled MPSoCs. To minimize hardware overhead, we employ Approximated Weighted Moving Average (WMA)-based computation scheme, ensuring a lightweight yet effective implementation. By defining a spectrum of abnormal behaviors, our system successfully detected and mitigated malicious temperature fluctuations, reducing cases from 3.00°C to 1.9°C. The anomaly detection module achieved an accuracy of up to 82% in detecting thermal attacks, which is only 10-15% less than top-performing Machine Learning (ML) models like Random Forest. However, our approach reduces hardware usage by up to 75% for logic resources and eliminates the need for specialized resources, making it significantly more efficient than ML-based solutions. This method offers a practical and low-cost solution for resource-constrained environments, ensuring resilience against thermal attacks while maintaining system performance.

Multi-Processor System-on-Chips (MPSoCs) are highly vulnerable to thermal attacks that manipulate dynamic thermal management systems. To counter this, we propose an adaptive real-time monitoring mechanism that detects abnormal thermal patterns in chip tiles. Our design space exploration helped identify key thermal features for an efficient anomaly detection module to be implemented at routers of network-enabled MPSoCs. To minimize hardware overhead, we employ weighted moving average (WMA) calculations and bit-shift operations, ensuring a lightweight yet effective implementation. By defining a spectrum of abnormal behaviors, our system successfully detects and mitigates malicious temperature fluctuations, reducing severe cases from 3.00°C to 1.9°C. The anomaly detection module achieves up to 82% of accuracy in detecting thermal attacks, which is only 10-15% less than top-performing machine learning (ML) models like Random Forest. However, our approach reduces hardware usage by up to 75% for logic resources and 100% for specialized resources, making it significantly more efficient than ML-based solutions. This method provides a practical, low-cost solution for resource-constrained environments, ensuring resilience against thermal attacks while maintaining system performance.

We present SEIF, an exploratory methodology for information flow verification based on symbolic execution. SEIF begins with a statically built overapproximation of the information flow through a design and uses guided symbolic execution to provide a more precise picture of how information flows from a given set of security critical signals. SEIF can recognize and eliminate non-flows with high precision and for the true flows can find the corresponding paths through the design state with high coverage. We evaluate SEIF on two open-source CPUs, an AES core, and the AKER access control module. SEIF can be used to find counterexamples to information flow properties, and also to explore all flows originating from a source signal of interest. SEIF accounts for 86–90% of statically identified possible flows in three open-source designs. SEIF’s search strategies enable exploring the designs for 10-12 clock cycles in 4-6 seconds on average, demonstrating that this new exploratory style of information flow analysis can be practical.

The articles in this special issue focus on ongoing research efforts in the development, use, and evaluation of emerging hardware features and techniques to improve system security. We have seen the emergence of new hardware features to improve software security by limiting memory access within an address space, such as Intel’s memory protection keys (MPKs) and extended page table (EPT) switching, among others. Researchers have also proposed hardware-assisted roots of trust using trusted execution environments (TEEs), such as Intel’s software guard extensions (SGXs), so some questions are what the utility is of such techniques and what limitations they still face. The papers in this special issue provide guidance in these areas, which can be helpful in examining future research directions and future applications of such techniques.

Using formal methods requires first developing the properties to be verified, which is a difficult and time-consuming task. This article describes our research on automating the property generation process for information-flow properties that are critical to the security of hardware designs.

This paper presents Coppelia, an end-to-end tool that, given a processor design and a set of security-critical assertions, automatically generates complete, replayable exploit programs to help designers find, contextualize, and assess the security threat of hardware vulnerabilities. In Coppelia, we develop a hardware-oriented backward symbolic execution engine with a new cycle stitching method and fast validation technique, along with several optimizations for exploit generation.