An asynchronous hierarchical router for networks‐on‐chip‐based three‐dimensional multi‐processor system‐on‐chip
Authors:
- 7 February 2012
- journal article
- research article
- Published by Wiley in Software: Practice and Experience
- Vol. 42 (7) , 877-890
Abstract
SUMMARY: Three‐dimensional networks‐on‐chip (3D NoC) are rising as a good approach to well managed complex interconnections in 3D multi‐processor system‐on‐chip (MPSoC). This paper introduces a new router in order to enhance throughput and latency compared to classic 3D mesh NoC. The proposed router is hierarchical as it is composed of two completely decoupled modules: one for inter‐layer communication and one for intra‐layer communication. It is fully implemented in asynchronous logic to allow low latency transfer.Synthesis and extrapolation results show that the hierarchical router is competitive with the classic 3D mesh in terms of area and power. Throughput and latency evaluation is performed using a SystemC‐TLM NoC simulator. Simulations' results show that the proposed hierarchical router can outperform the 3D mesh by more than 25% in terms of throughput and latency in the case of transpose traffic. Copyright © 2012 John Wiley & Sons, Ltd.Keywords
This publication has 16 references indexed in Scilit:
- A fully-asynchronous low-power framework for GALS NoC integration2010
- An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application2009
- De Bruijn graph based 3D Network on Chip architecture design2009
- A low-radix and low-diameter 3D interconnection network design2009
- Synthesis of networks on chips for 3D systems on chips2009
- Design of application-specific 3D Networks-on-Chip architectures2008
- MIRA: A Multi-layered On-Chip Interconnect Router Architecture2008
- Die Stacking (3D) Microarchitecture2006
- Design and Management of 3D Chip Multiprocessors Using Network-in-Memory2006
- An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework2005