On-chip measurement to analyze failure mechanisms of ICs under system level ESD stress
Authors:
- F. CaigneťFCF. Caigneť
- N. NolhierNNN. Nolhier
- M. BafleurMBM. Bafleur
- A. WangAWA. Wang
- N. MauranNMN. Mauran
- 1 September 2013
- journal article
- Published by Elsevier in Microelectronics Reliability
- Vol. 53 (9-11) , 1278-1283
Abstract
No abstract availableKeywords
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