On-chip measurement to analyze failure mechanisms of ICs under system level ESD stress

Authors:
  • FCF. Caigneť
    F. Caigneť
  • NNN. Nolhier
    N. Nolhier
  • MBM. Bafleur
    M. Bafleur
  • AWA. Wang
    A. Wang
  • NMN. Mauran
    N. Mauran

Abstract
No abstract available

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