Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology
- 23 September 2020
- journal article
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 67 (11) , 4631-4635
Abstract
This article explores the feasibility of high-temperature annealing for top-tier devices in a sequential 3-D (Seq3D) technology. Thermally stable bottom-tier device and interconnect design guidelines are provided. CMOS-SRAM partitioning is proposed to achieve performance gain from Seq3-D. The implications of thermally stable Seq3-D on system-level performance are evaluated. Seq3-D wafer and die cost of ownership are estimated.Keywords
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